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| december 2012 doc id 022691 rev 3 1/128 1 STM32F372XX stm32f373xx arm cortex-m4f 32b mcu+fpu, up to 256kb flash+32kb sram timers, 4 adcs (12/16-bit), 3 dacs, 2 comp., 2.0-3.6 v operation datasheet ? production data features core: arm 32-bit cort ex?-m4f cpu (72 mhz max), single-cycle mu ltiplication and hw division, dsp instructio n with fpu (floating- point unit) and mpu (memory protection unit) memories ? 64 to 256 kbytes of flash memory ? 32 kbytes of sram with hw parity check crc calculation unit reset and power management ? voltage range: 2.0 to 3.6 v ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop, standby ?v bat supply for rtc and backup registers clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x16 pll option ? internal 40 khz oscillator up to 84 fast i/os ? all mappable on external interrupt vectors ? up to 45 i/os with 5 v tolerant capability 12-channel dma controller one 12-bit, 1.0 s adc (up to 16 channels) ? conversion range: 0 to 3.6 v ? separate analog supply from 2.4 up to 3.6 up to three 16-bit sigma delta adc ? separate analog supply from 2.2 to 3.6 v, up to 21 single/ 11 diff channels up to three 12-bit dac channels two fast rail-to-rail analog comparators with programmable input and output up to 24 capacitive sensing channels supporting touchkey, linear and rotary touchsensors 17 timers ? two 32-bit timer and three 16-bit timers with up to 4 ic/oc/pwm or pulse counter ? two 16-bit timers with up to 2 ic/oc/pwm or pulse counter ? four 16-bit timers with up to 1 ic/oc/pwm or pulse counter ? independent and system watchdog timers ? systick timer: 24-bit downcounter ? three 16-bit basic timers to drive the dac calendar rtc with alarm and periodic wakeup from stop/standby communication interfaces ? can interface (2.0b active) ?two i 2 c interfaces; supporting fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, wakeup from stop ? three usarts supporting master synchronous spi and modem control; with iso7816 interface, lin, irda capability, auto baud rate detection, wakeup feature ? three spis (18 mbit/s) with 4 to 16 programmable bit frame, muxed i2s ? hdmi-cec bus interface ? usb 2.0 full speed interface serial wire devices, jtag, cortex-m4f etm 96-bit unique id table 1. device summary reference part number STM32F372XX stm32f372c8, stm32f372r8, stm32f372v8, stm32f372cb, stm32f372rb, stm32f372vb, stm32f372cc, stm32f372rc, stm32f372vc stm32f373xx stm32f373c8, stm32f373r8, stm32f373v8, stm32f373cb, stm32f373rb, stm32f373vb, stm32f373cc, stm32f373rc, stm32f373vc lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp48 (7 7 mm) fbga ufbga100 (7 x 7 mm) www.st.com
contents stm32f37x 2/128 doc id 022691 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm? cortex?-m4f core with embedded flash and sram . . . . . . . . . 12 3.2 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 cyclic redundancy check (crc) calculation uni t . . . . . . . . . . . . . . . . . . . 13 3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 3.11.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 3.12 12-bit analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.13 16-bit sigma delta analog-to-digital converters (sdadc) . . . . . . . . . . . . . 18 3.14 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.16 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.17 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.17.1 general-purpose timers (tim2 to tim5, tim12 to tim17, tim19) . . . . . 22 stm32f37x contents doc id 022691 rev 3 3/128 3.17.2 basic timers (tim6, tim7, tim18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17.3 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.4 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.19 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20 universal synchronous/asynchronous receiver transmitter (usart) . . . 25 3.21 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) . 25 3.22 high-definition multimedia interface (hdmi) - consumer electronics control (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.23 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.24 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.25 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.26 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 56 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 57 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 contents stm32f37x 4/128 doc id 022691 rev 3 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.8 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.15 nrst characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.16 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.17 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.18 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.19 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.20 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.21 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.22 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.23 usb characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.24 can (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.25 sdadc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 122 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 stm32f37x list of tables doc id 022691 rev 3 5/128 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. capacitive sensing gpios available on stm32f37x devices . . . . . . . . . . . . . . . . . . . . . . 20 table 4. no. of capacitive sensing channels available on stm32f37x devices. . . . . . . . . . . . . . . . 21 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. comparison of i 2 c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. stm32f37x i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. stm32f37x usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. stm32f37x spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. stm32f37x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. alternate functions for port pa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. alternate functions for port pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. alternate functions for port pc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. alternate functions for port pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. alternate functions for port pe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 17. alternate functions for port pf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. stm32f37x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 24. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 25. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 26. embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 27. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 table 28. typical and maximum current consumption from v dd supply at v dd = 3.6 v . . . . . . . . . . 59 table 29. typical and maximum current consumption from v dda supply . . . . . . . . . . . . . . . . . . . . . 61 table 30. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 61 table 31. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 62 table 32. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 62 table 33. typical current consumption in run mode, code with data processi ng running from flash 64 table 34. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 65 table 35. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 42. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 43. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 44. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 45. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 46. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 47. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 48. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 list of tables stm32f37x 6/128 doc id 022691 rev 3 table 49. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 50. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 51. i/o current injection susceptibilit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 52. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 53. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 54. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 57. i 2 c analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 58. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 59. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 60. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 61. r src max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 62. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 63. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 64. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 65. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 66. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 67. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 68. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 69. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 70. wwdg min-max timeout value @72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 71. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 72. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 73. usb: full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 table 74. sdadc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 75. vrefsd+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 76. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 77. lqpf100 ? 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . 115 table 78. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 117 table 79. lqfp48 ? 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 119 table 80. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 81. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 82. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 stm32f37x list of figures doc id 022691 rev 3 7/128 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. stm32f37x lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 3. stm32f37x lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 4. stm32f37x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5. stm32f37x bga100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. stm32f37x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 11. typical v bat current consumption (lse and rtc on/lsedrv[1:0]='00') . . . . . . . . . . . . 63 figure 12. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 13. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 14. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 15. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 16. hsi oscillator accuracy characte rization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 17. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 18. tc and tta i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 19. five volt tolerant (ft and ftf) i/o input characteristics - cmos port. . . . . . . . . . . . . . . . . 84 figure 20. five volt tolerant (ft and ftf) i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . 84 figure 21. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 22. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 23. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 24. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 25. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 26. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 27. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 28. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 29. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 30. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 31. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 32. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 33. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 34. lqfp100 ?14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 115 figure 35. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 36. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 117 figure 37. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 38. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 119 figure 39. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 40. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 introduction stm32f37x 8/128 doc id 022691 rev 3 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f37x microcontrollers. this stm32f37x datasheet should be read in conjunction with the stm32f37x reference manual. the reference manual is available from the stmicroelectronics website www.st.com. for information on the cortex?-m4f core please refer to the cortex?-m4f technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.cortexm.m4/index.html and also refer to the stm32f3xxx and stm32f4xxx cortex-m4 programming manual (pm0214) at address: http://www.st.com/in ternet/com/technical_resou rces/technical_literature/ programming_manual/dm00046982.pdf stm32f37x description doc id 022691 rev 3 9/128 2 description the stm32f37x family is based on the high-performance arm? cortex?-m4f 32-bit risc core operating at a frequency of up to 72 mhz, and embedding a floating point unit (fpu), a memory protection unit (mpu) and an embedded trace macrocell (etm). the family incorporates high-speed embedded memories (up to 256 kbyte of flash memory, up to 32 kbytes of sram), and an extensive range of enhanced i/os and peripherals connected to two apb buses. the stm32f37x devices offer one fast 12-bit adc (1 msps), up to three 16-bit sigma delta adcs, up to two comparators, up to two dacs (dac1 with 2 channels and dac2 with 1 channel), a low-power rtc, 9 general-purpose 16-bit timers, two general-purpose 32-bit timers, three basic timers. they also feature standard and advanced communication interfaces: up to two i2cs, three spis, all with muxed i2ss, three usarts, can and usb. the stm32f37x family operates in the -40 to +85 c and -40 to +105 c temperature ranges from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f37x family offers devices in five packages ranging from 48 pins to 100 pins. the set of included peripherals changes with the device chosen. description stm32f37x 10/128 doc id 022691 rev 3 table 2. device overview peripheral stm32f 372cx stm32f 372rx stm32f 372vx stm32f 373cx stm32f 373rx stm32f 373vx flash (kbytes) 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 sram (kbytes) 16 24 32 16 24 32 16 24 32 16 24 32 16 24 32 16 24 32 timers general purpose 9 (16-bit) 2 (32 bit) 9 (16-bit) 2 (32 bit) basic 3 (16-bit) 3 (16-bit) comm. interfaces spi/i2s 3 3 i 2 c2 2 usart 3 3 can 1 1 usb 1 1 gpios normal i/os (tc, tta) 36 52 84 36 52 84 5 volts to l e r a n t i/os (ft, ftf) 20 28 45 20 28 45 12-bit adcs 1 1 16-bit adcs sigma- delta 1 (sdadc1) 3 12-bit dacs outputs 1 (dac2) 3 analog comparator 1 (comp1) 2 capacitive sensing channels 14 17 24 14 17 24 max. cpu frequency 72 mhz 72 mhz main operating voltage 2.0 to 3.6 v 2.0 to 3.6 v 16-bit sdadc operating voltage 2.2 to 3.6 v 2.2 to 3.6 v operating temperature ambient operating temperature: ? 40 to 85 c / ? 40 to 105 c junction temperature: ? 40 to 125 c ambient operating temperature: ? 40 to 85 c / ? 40 to 105 c junction temperature: ? 40 to 125 c packages lqfp48 lqfp64 lqfp100, ufbga100 (1) lqfp48 lqfp64 lqfp100, ufbga100 (1) 1. ufbga100 package availabl e on 256-kb versions only. stm32f37x description doc id 022691 rev 3 11/128 figure 1. block diagram 1. af: alternate function on i/o pins. 2. example given for stm32f373xx device. 0 ! ; = % 8 4 ) 4 7 7 $ ' . 6 ) # b i t ! $ # * 4 ! ' 3 7 ! ) . s * 4 $ ) * 4 # + 3 7 # , + * 4 - 3 3 7 $ ! 4 * 4 2 3 4 * 4 $ / . 2 % 3 % 4 6 $ $ t o 6 8 8 ! & 0 " ; = 0 # ; = ! ( " t o 5 3 " & 3 # ! . 4 8 # ! . 2 8 - / 3 ) - ) 3 / 3 2 ! - 2x(8x16bit) 7 + 5 0 f max - ( z 6 ss 3 # , 3 $ ! 3 - " ! ) # 6 2 % & $ - ! 4 ) - 4 ) - 8 4 ! , / 3 # - ( z 8 4 ! , k ( z / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? / 5 4 / 3 # ? ) . ! 0 " & max - ( z ( # , + - ! . ! ' 4 ! 0 " 0 # , + a s ! & & l a s h u p t o + " 6 / , 4 2 % ' 6 4 / 6 6 dd18 0 / 7 % 2 " a c k u p i n t e r f a c e a s ! & " u s - a t r i x b i t ) n t e r f a c e u p t o + " 2 4 # # / 2 4 % 8 - & # 0 5 ) b u s $ b u s 0 b u s o b l & l a s h 4 r a c e # o n t r o l l e r 5 3 ! 2 4 5 3 ! 2 4 3 0 ) ) 3 c h a n n e l s " a c k u p r e g 3 # , 3 $ ! 3 - " ! ) # a s ! & 2 8 4 8 # 4 3 2 4 3 5 3 ! 2 4 4 e m p s e n s o r 6 2 % & 0 $ ; = 0 % ; = # h a n n e l s % 4 2 # h a n n e l s % 4 2 & # , + 3 t a n d b y ) 7 $ ' @v ddio @vsw 0 / 2 0 $ 2 3 5 0 0 , 9 @v dda 6 $ $ ! 6 3 3 ! 6 " ! 4 3 m a r t # a r d a s ! & 2 8 4 8 # 4 3 2 4 3 3 m a r t # a r d a s ! & 2 8 4 8 # 4 3 2 4 3 3 m a r t # a r d a s ! & ! 0 " & max - ( z . 6 ) # 3 0 ) ) 3 - / 3 ) - ) 3 / 3 # + . 3 3 a s ! & ) & i n t e r f a c e 3 5 0 % 2 6 ) 3 ) / . 0 6 $ 2 e s e t ) n t @ vddio ! ( " t o ! 0 " ! 0 " ! 7 5 0 / 2 ! . 4 ) 4 ! - 0 3 y s t e m 0 & ; b i t s = 3 # + . 3 3 a s ! & - / 3 ) - ) 3 / 2x(8x16bit) 3 0 ) ) 3 3 # + . 3 3 a s ! & 2 % 3 % 4 # , / # + # 4 2 , ! 0 " 0 # , + b i t $ ! # ? / 5 4 ) & @vdda $ ! # ? / 5 4 a s ! & $ ! # ? / 5 4 a s ! & 5 3 ! 2 4 # , + # % # # , + ! $ # # , + 3 $ ! $ # crc ! ( " ' 0 ) / 0 / 2 4 ! ' 0 ) / 0 / 2 4 " ' 0 ) / 0 / 2 4 # ' 0 ) / 0 / 2 4 $ ' 0 ) / 0 / 2 4 % ' 0 ) / 0 / 2 4 & a s ! & a s ! & 4 ) - 4 ) - 4 ) - # h a n n e l s # h a n n e l s # h a n n e l # o m p # h a n n e l " 2 + a s ! & # o m p # h a n n e l " 2 + a s ! & # o m p # h a n n e l " 2 + a s ! & ( $ - ) # % # ( $ - ) # % # a s ! & $ ! # ? / 5 4 a s ! & 4 ) - 4 ) - 4 ) - @vdda b i t 3 $ ! $ # 6 2 % & 3 $ 6 2 % & 3 $ ) & @vddsd3 b i t 3 $ ! $ # ) & @vddsd12 b i t 3 $ ! $ # ) & 3 $ ! $ # ) . s 3 $ ! $ # ) . s s h a r e d w 3 $ ! $ # ) . s s h a r e d w 3 $ 6 $ $ 3 $ 6 $ $ 3 $ # / - 0 @vdd # / - 0 3 9 3 # & ' # 4 , ) . s / 5 4 s a s ! & 4 o u c h 3 e n s i n g # o n t r o l l e r ' r o u p s o f c h a n n e l s m a x 4 ) - # h a n n e l s % 4 2 a s ! & 4 ) - # h a n n e l s % 4 2 a s ! & b x # ! . $ - ! tim 19 4 c h a n n e ls, etr 2 c h a n n e l etr 3 2 ! - " c h a n n e l s 4 ) - 2 # h a n n e l a s ! & 4 ) - 4 ) - # h a n n e l a s ! & a s ! & 3 $ ! $ # as af as af # , + 5 3 " ? $ - 5 3 " ? $ 0 6 3 3 3 $ ! ( " & m a x - ( z b i t $ ! # ? / 5 4 ) & b i t $ ! # ? / 5 4 ) & . 4 7 2 # , 3 @v dda 0 , , 2 # ( 3 - ( z functional overview stm32f37x 12/128 doc id 022691 rev 3 3 functional overview 3.1 arm? cortex?-m4f core wi th embedded flash and sram the arm cortex-m4f processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m4f 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructi ons which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32f37x family is compatible with all arm tools and software. figure 1 shows the general block diagram of the stm32f37x family. 3.2 memory protection unit the memory protection unit (mpu) is used to separate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically upd ate the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. the cortex-m4f processor is a high performance 32-bit processor designed for the microcontroller market. it offers significant benefits to developers, including: outstanding processing performance combined with fast interrupt handling enhanced system debug with extensiv e breakpoint and trace capabilities efficient processor core, system and memories ultralow power consumption with integrated sleep modes platform security robustness with optional integrated memory protection unit (mpu). with its embedded arm core, the stm32f37x devices are compatible with all arm development tools and software. stm32f37x functional overview doc id 022691 rev 3 13/128 3.3 embedded flash memory all stm32f37x devices feature up to 256 kbytes of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). 3.4 cyclic redundancy ch eck (crc) calculation unit the crc (cyclic redundancy check) calculatio n unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 embedded sram all stm32f37x devices feature up to 32 kbytes of embedded sram with hardware parity check. the memory can be accessed in read/write at cpu clock speed with 0 wait states. 3.6 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart2 (pd5/pd6) or usb (pa11/pa12) through dfu (device firmware upgrade). functional overview stm32f37x 14/128 doc id 022691 rev 3 3.7 power management 3.7.1 power supply schemes v dd : external power supply for i/os and the internal regulator. it is provided externally through v dd pins, and can be 2.0 to 3.6 v. v dda = 2.0 to 3.6 v: ? external analog power supplies for reset blocks, rcs and pll ? supply voltage for 12-bit adc, dacs and comparators (minimum voltage to be applied to v dda is 2.4 v when the 12-bit adc and dac are used). v ddsd12 and v ddsd3 = 2.2 to 3.6 v: supply voltages for sdadc1/2 and sdadcd3 sigma delta adcs. independent from v dd /v dda . v bat = 1.65 to 3.6 v: power supply for rtc, ex ternal clock 32 khz oscillator and backup registers when v dd is not present. 3.7.2 power supply supervisor the device has an integrated power-on reset (por)/power-down reset (pdr) circuitry. it is always active, and ensures proper oper ation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.7.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr), and power-down. the mr mode is used in the nominal regulation mode (run) the lpr mode is used in stop mode. the power-down mode is used in standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. stm32f37x functional overview doc id 022691 rev 3 15/128 3.7.4 low-power modes the stm32f37x supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the usarts, the i2cs, the cec, the usb wakeup, and the rtc alarm. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.8 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the hi gh speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the high speed apb domains is 72 mhz, while the maximum allowed fr equency of the low speed apb domain is 36 mhz. 3.9 general-purpose input/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. functional overview stm32f37x 16/128 doc id 022691 rev 3 do not reconfigure gpio pins which are not present on 48 and 64 pin packages to the analog mode. additional current consumption in the range of tens of a per pin can be observed if v dda is higher than v ddio . 3.10 direct memory access (dma) the flexible 12-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the two dmas can be used with the main peripherals: spis, i2cs, usarts, dacs, adc, sdadcs, general-purpose timers. 3.11 interrupts and events 3.11.1 nested vectored interrupt controller (nvic) the stm32f37x devices embed a nested vectored interrupt controller (nvic) able to handle up to 60 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. 3.11.2 extended interrupt /event controller (exti) the extended interrupt/event controller consists of 29 edge detector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trigge r event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 84 gpios can be connected to the 16 external interrupt lines. stm32f37x functional overview doc id 022691 rev 3 17/128 3.12 12-bit analog-to-digital converter (adc) the 12-bit analog-to-digital converter is based on a successive approximation register (sar) architecture. it has up to 16 external channels (ain15:0) and 3 internal channels (temperature sensor, voltage reference, v bat voltage measurement) performing conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the timers (timx) can be internally connected to the adc start and injection trigger, respectively, to allow the application to synchronize a/d conversion and timers. 3.12.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperat ure sensor measurement, each device is individually factory-calibrated by st. the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. see ta b l e 6 5 : temperature sensor calibration values on page 103 . 3.12.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to the adc_in17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. 3.12.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a divider by 2. as a consequence, the converte d digital value is half the v bat voltage. functional overview stm32f37x 18/128 doc id 022691 rev 3 3.13 16-bit sigma delta analog-to-digital converters (sdadc) up to three 16-bit sigma-delta analog-to-digital converters are embedded in the stm32f37x. they have up to two separate supply voltages allowing the analog function voltage range to be independent from the stm32f37x power supply. they share up to 21 input pins which may be configured in any combination of single-ended (up to 21) or differential inputs (up to 11). the conversion speed is up to 16.6 ksps for each sdadc when converting multiple channels and up to 50 ksps per sdadc if single channel conversion is used. there are two conversion modes: single conversion mode or continuous mode, capable of automatically scanning any number of channels. the data can be automatically stored in a system ram buffer, reducing the software overhead. a timer triggering system can be used in order to control the start of conversion of the three sdadcs and/or the 12-bit fast adc. this timing control is very flexible, capable of triggering simultaneous conversions or inserting a programmable delay between the adcs. up to two external reference pins (vre fsd+, vrefsd-) and an internal 1.2/1.8 v reference can be used in conjunction with a programmable gain (x0.5 to x32) in order to fine-tune the input voltage range of the sdadc. stm32f37x functional overview doc id 022691 rev 3 19/128 3.14 digital-to-analog converter (dac) the devices feature up to two 12-bit buffered dacs with three output channels that can be used to convert three digital signals into three analog voltage signal outputs. the internal structure is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supports the following features: up to two dac converters with three output channels: ? dac1 with two output channels ? dac2 with one output channel. 8-bit or 10-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions (dac1 only) dma capability for each channel external triggers for conversion 3.15 fast comparators (comp) the stm32f37x embeds up to 2 comparators with rail-to-rail inputs and high-speed output. the reference voltage can be internal or external (delivered by an i/o). the threshold can be one of the following: dacs channel outputs external i/o internal reference voltage (v refint ) or submultiple (1/4 v refint , 1/2 v refint and 3/4 v refint ) the comparators can be combined into a window comparator. both comparators can wake up the device from stop mode and generate interrupts and breaks for the timers. functional overview stm32f37x 20/128 doc id 022691 rev 3 3.16 touch sensing controller (tsc) the devices provide a simple solution for adding capacitive sensing functionality to any application. capacitive sensing technology is able to detect the presence of a finger near an electrode which is protected from direct touc h by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge tr ansfer acquisition prin ciple. it consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. to limit the cpu bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. up to 24 touch sensing electrodes can be controlled by the tsc. the touch sensing i/os are organized in 8 acquisition groups, with up to 4 i/os in each group. table 3. capacitive sensing gpios available on stm32f37x devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 5 tsc_g5_io1 pb3 tsc_g1_io2 pa1 tsc_g5_io2 pb4 tsc_g1_io3 pa2 tsc_g5_io3 pb6 tsc_g1_io4 pa3 tsc_g5_io4 pb7 2 tsc_g2_io1 pa4 6 tsc_g6_io1 pb14 tsc_g2_io2 pa5 tsc_g6_io2 pb15 tsc_g2_io3 pa6 tsc_g6_io3 pd8 tsc_g2_io4 pa7 tsc_g6_io4 pd9 3 tsc_g3_io1 pc4 7 tsc_g7_io1 pe2 tsc_g3_io2 pc5 tsc_g7_io2 pe3 tsc_g3_io3 pb0 tsc_g7_io3 pe4 tsc_g3_io4 pb1 tsc_g7_io4 pe5 4 tsc_g4_io1 pa9 8 tsc_g8_io1 pd12 tsc_g4_io2 pa10 tsc_g8_io2 pd13 tsc_g4_io3 pa13 tsc_g8_io3 pd14 tsc_g4_io4 pa14 tsc_g8_io4 pd15 stm32f37x functional overview doc id 022691 rev 3 21/128 3.17 timers and watchdogs the stm32f37x includes two 32-bit and nine 16-bit general-purpose timers, three basic timers, two watchdog timers and a systick timer. the table below compares the features of the advanced control, general purpose and basic timers. table 4. no. of capacitive sensing channels available on stm32f37x devices analog i/o group number of capacitive sensing channels stm32f37xcx stm32f37xrx stm32f37xvx g1 3 3 3 g2 2 3 3 g3 1 3 3 g4 3 3 3 g5 3 3 3 g6 2 2 3 g7 0 0 3 g8 0 0 3 number of capacitive sensing channels 14 17 24 table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs general- purpose tim2 tim5 32-bit up, down, up/down any integer between 1 and 65536 ye s 4 0 general- purpose tim3, tim4, tim19 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 0 general- purpose tim12 16-bit up any integer between 1 and 65536 no 2 0 general- purpose tim15 16-bit up any integer between 1 and 65536 ye s 2 1 general- purpose tim13, tim14 16-bit up any integer between 1 and 65536 no 1 0 functional overview stm32f37x 22/128 doc id 022691 rev 3 3.17.1 general-purpose timers (tim2 to tim5, tim12 to tim17, tim19) there are eleven synchronizable general-purpose timers embedded in the stm32f37x (see ta bl e 5 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. tim2, 3, 4, 5 and 19 these five timers are full-featured general-purpose timers: ? tim2 and tim5 have 32-bit auto-reload up/downcounters and 32-bit prescalers ? tim3, 4, and 19 have 16-bit auto-reload up/downcounters and 16-bit prescalers these timers all feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. they can work together, or with the other general- purpose timers via the timer link featur e for synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generation and support quadrature encoders. tim12, 13, 14, 15, 16, 17 these six timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim12 has 2 channels ? tim13 and tim14 have 1 channel ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.17.2 basic timers (tim6, tim7, tim18) these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 ye s 1 1 basic tim6, tim7, tim18 16-bit up any integer between 1 and 65536 ye s 0 0 table 5. timer feature comparison (continued) timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs stm32f37x functional overview doc id 022691 rev 3 23/128 3.17.3 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.17.4 system windo w watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb1 clock (pclk1) derived from the main clock. it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.17.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0 programmable clock source 3.18 real-time clock (rtc) and backup registers the rtc and the backup registers are supplied through a switch that takes power either from v dd supply when present or through the v bat pin. the backup registers are thirty two 32-bit registers used to store 128 bytes of user application data. they are not reset by a system or power reset, and they are not reset when the device wakes up from the standby mode. the rtc is an independent bcd timer/counter. its main features are the following: calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. automatic correction for 28th, 29th (leap year), 30th and 31st day of the month. 2 programmable alarms with wake up from stop and standby mode capability. periodic wakeup unit with programmable resolution and period. on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. 3 anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. functional overview stm32f37x 24/128 doc id 022691 rev 3 the rtc clock sources can be: a 32.768 khz external crystal a resonator or oscillator the internal low-power rc oscillator (typical frequency of 40 khz) the high-speed external clock divided by 32 3.19 inter-integrated circuit interface (i 2 c) up to two i 2 c bus interfaces can operate in multimaster and slave modes. they can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes with 20 ma output drive. they support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, they provide hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeout verifications and alert protocol management. they also have a clock domain independent from the cpu clock, allowing the application to wake up the mcu from stop mode on address match. the i 2 c interfaces can be served by the dma controller refer to ta b l e 7 for the differences between i2c1 and i2c2. table 6. comparison of i 2 c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i 2 c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled table 7. stm32f37x i 2 c implementation i 2 c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode x x 10-bit addressing mode x x standard mode (up to 100 kbit/s) x x fast mode (up to 400 kbit/s) x x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x x independent clock x x smbus x x wakeup from stop x x stm32f37x functional overview doc id 022691 rev 3 25/128 3.20 universal synchronous/asynchronous receiver transmitter (usart) the stm32f37x embeds three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3). all usarts interfaces are able to communicate at speeds of up to 9 mbit/s. they provide hardware management of the cts and rts signals, they support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode, smart card mode (iso 7816 compliant), autobaudrate feature and have lin master/slave capability. the usar t interfaces can be served by the dma controller. refer to ta b l e 8 for the features of usart1, usart2 and usart3. 3.21 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) up to three spis are able to communicate at up to 18 mbits/s in slave and master modes in full-duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. the spis can be served by the dma controller. three standard i 2 s interfaces (multiplexed with spi1, spi2 and spi3) are available, that can be operated in master or slave mode. these in terfaces can be configured to operate with 16/32 bit resolution, as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in table 8. stm32f37x usart implementation usart modes/features (1) 1. x = supported. usart1 usart2 usart3 hardware flow co ntrol for modem x x x continuous communication using dma x x x multiprocessor communication x x x synchronous mode x x x smartcard mode x x x single-wire half-duplex communication x x x irda sir endec block x x x lin mode x x x dual clock domain and wakeup from stop mode x x x receiver timeout interrupt x x x modbus communication x x x auto baud rate detection x x x driver enable x x x functional overview stm32f37x 26/128 doc id 022691 rev 3 master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. refer to ta b l e 9 for the features between spi1 and spi2. 3.22 high-definition multimedia interface (hdmi) - consumer electronics control (cec) the device embeds a hdmi-cec controller that provides hardware support for the consumer electronics control (cec) protocol (supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. it has a clock domain independent from the cpu clock, allowing the hdmi_cec controller to wakeup the mcu from stop mode on data reception. 3.23 controller area network (can) the can is compliant with specifications 2.0a and b (active) with a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.24 universal serial bus (usb) the stm32f37x embeds an usb device peripheral compatible with the usb full-speed 12 mbs. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator). table 9. stm32f37x spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 spi3 hardware crc calculation x x x rx/tx fifo x x x nss pulse mode x x x i2s mode xxx ti mode xxx stm32f37x functional overview doc id 022691 rev 3 27/128 3.25 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.26 embedded trace macrocell? the arm embedded trace macrocell provides a great er visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f37x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. pinouts and pin description stm32f37x 28/128 doc id 022691 rev 3 4 pinouts and pin description figure 2. stm32f37x lqfp48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 21 22 23 24 17 18 19 20 2 3 4 5 6 7 8 9 10 11 vbat pc14 - osc32_in pc15 - osc32_out nrst vssa/vref- vdda/vref+ pa0 pa1 pa2 vdd_1 vss_1 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 pf7 pf6 pa13 pa12 pa11 pa10 pa 9 pa 8 pd8 pb15 pb14 vrefsd+ pa 3 pa 4 pa 5 pa6 vdd_2 pb0 pb1 pb2 pe8 vsssd/vrefsd- pe9 vddsd pf0-osc_in pf1-osc_out pc13 12 1 . 4 7 , 1 & 0 stm32f37x pinouts and pin description doc id 022691 rev 3 29/128 figure 3. stm32f37x lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc14 - osc32_in pc15 - osc32_out nrst pc0 pc1 pc2 pc3 vssa/vref- vdda pa0 pa1 pa2 vdd_1 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 pf7 pf6 pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pd8 pb15 pb14 vrefsd+ pa3 vref+ vdd_2 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pe8 pf1 - osc_out pf0 - osc_in pc13 vss_1 pe9 vsssd/vrefsd- vddsd , 1 & 0 - 3 6 pinouts and pin description stm32f37x 30/128 doc id 022691 rev 3 figure 4. stm32f37x lqfp100 pinout 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 0 & 0 & 0 & / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 0 & 6 3 3 ! 6 2 % & 6 2 % & 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ ? 6 3 3 ? 0 & 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 6 2 % & 3 $ 6 $ $ 3 $ 0 ! 0 & 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 6 2 % & 3 $ 6 3 3 3 $ 6 $ $ 3 $ 6 $ $ ? 6 3 3 ? 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! - 3 6 , 1 & 0 0 # 0 & / 3 # ? / 5 4 stm32f37x pinouts and pin description doc id 022691 rev 3 31/128 figure 5. stm32f37x bga100 pinout - 3 6 ! " % $ # & ' ( * + , - 0 % 0 # 0 # 0 % 0 # 0 & 6 3 3 ! 6 2 % & 6 2 % & 6 $ $ ! 0 % 0 % 0 % 0 % 6 " ! 4 0 & 0 & . 2 3 4 0 # 0 # 0 ! 0 ! 0 " 0 % 0 " 6 3 3 ? 0 & 6 $ $ ? 0 # 0 ! 0 ! 0 ! " / / 4 0 " 6 $ $ ? 0 ! 0 ! 0 ! 0 $ 0 " 0 " 0 # 0 # 0 " 0 $ 0 $ 0 " 0 " 0 " 0 $ 0 % 0 % 0 " 0 $ 0 $ 0 $ 0 % 0 % 0 ! 0 $ 0 $ 0 $ 0 % 0 % 0 ! 0 # 0 # 0 # 0 ! 0 $ 0 $ 0 " 0 " 0 % 0 ! 0 # 0 & 0 ! 0 # 0 $ 0 $ 0 " 6 2 % & 3 $ 0 % 6 3 3 ? 6 $ $ ? 0 ! 0 ! 0 ! 0 # 0 # 0 $ 0 $ 6 2 % & 3 $ 6 $ $ 3 $ 0 % 6 3 3 3 $ 6 $ $ 3 $ 0 # 0 & 0 & pinouts and pin description stm32f37x 32/128 doc id 022691 rev 3 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3 v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 11. stm32f37x pin definitions pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions 1 b2 pe2 i/o ft (1) tsc_g7_io1, traceclk 2 a1 pe3 i/o ft (1) tsc_g7_io2, traced0 3 b1 pe4 i/o ft (1) tsc_g7_io3, traced1 4 c2 pe5 i/o ft (1) tsc_g7_io4, traced2 5 d2 pe6 i/o ft (1) traced3 wkup3, rtc_tamper3 6 e2 1 1 vbat s backup power supply 7c122 pc13 i/otc wkup2_alarm_out_ calib_out_timestamp, rtc_tamper1 8d133 pc14 - osc32_in i/o tc osc32_in 9e144 pc15 - osc32_out i/o tc osc32_out 10 f2 pf9 i/o ft (1) tim14_ch1 stm32f37x pinouts and pin description doc id 022691 rev 3 33/128 11 g2 pf10 i/o ft (1) 12 f1 5 5 pf0 - osc_in i/o ftf i2c2_sda osc_in 13 g1 6 6 pf1 - osc_out i/o ftf i2c2_scl osc_out 14 h2 7 7 nrst i/o rst device reset input / internal reset output (active low) 15 h1 8 pc0 i/o tta (1) tim5_ch1_etr adc_in10 16 j2 9 pc1 i/o tta (1) tim5_ch2 adcin11 17 j3 10 pc2 i/o tta (1) spi2_miso/i2s2_mck, tim5_ch3 adc_in12 18 k2 11 pc3 i/o tta (1) spi2_mosi/i2s2_sd, tim5_ch4 adc_in13 19 j1 pf2 i/o ft (1) i2c2_smba 20 k1 12 8 vssa/vref- s analog ground 9 vdda/vref+ s (1) analog power supply / reference voltage for adc, comp, dac 21 m1 13 vdda s (1) analog power supply 22 l1 17 vref+ s (1) reference voltage for adc, comp, dac 23 l2 14 10 pa0 i/o tta usart2_cts, tim2_ch1_etr, tim5_ch1_etr, tim19_ch1, tsc_g1_io1, comp1_out rtc_ tamper2, wkup1, adc_in0, comp1_inm 24 m2 15 11 pa1 i/o tta spi3_sck/i2s3_ck, usart2_rts, tim2_ch2, tim15_ch1n, tim5_ch2, tim19_ch2, tsc_g1_io2, adc_in1, comp1_inp, rtc_ref_clk_in 25 k3 16 12 pa2 i/o tta comp2_out, spi3_miso/i2s3_mck, usart2_tx, tim2_ch3, tim15_ch1, tim5_ch3, tim19_ch3, tsc_g1_io3 adc_in2, comp2_inm 26 l3 18 13 pa3 i/o tta spi3_mosi/i2s3_sd, usart2_rx, tim2_ch4, tim15_ch2, tim5_ch4, tim19_ch4, tsc_g1_io4 adc_in3, comp2_inp 27 e3 pf4 i/o ft (1) 28 h3 19 17 vdd_2 s digital power supply table 11. stm32f37x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions pinouts and pin description stm32f37x 34/128 doc id 022691 rev 3 29 m3 20 14 pa4 i/o tta spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, usart2_ck, tim3_ch2, tim12_ch1, tsc_g2_io1, adc_in4, dac1_out1 30 k4 21 15 pa5 i/o tta spi1_sck/i2s1_ck, cec, tim2_ch1_etr, tim14_ch1, tim12_ch2, tsc_g2_io2 adc_in5, dac1_out2 31 l4 22 16 pa6 i/o tta spi1_miso/i2s1_mck, comp1_out, tim3_ch1, tim13_ch1, tim16_ch1, tsc_g2_io3 adc_in6, dac2_out1, 32 m4 23 pa7 i/o tta (1) tsc_g2_io4, tim14_ch1, spi1_mosi/i2s1_sd, tim17_ch1, tim3_ch2, comp2_out adc_in7 33 k5 24 pc4 i/o tta (1) tim13_ch1, tsc_g3_io1, usart1_tx adc_in14 34 l5 25 pc5 i/o tta (1) tsc_g3_io2, usart1_rx adc_in15 35 m5 26 18 pb0 i/o tta spi1_mosi/i2s1_sd, tim3_ch3, tsc_g3_io3, tim3_ch2 adc_in8, sdadc1_ain6p 36 m6 27 19 pb1 i/o tta tim3_ch4, tsc_g3_io4 adc_in9, sdadc1_ain5p, sdadc1_ain6m 37 l6 28 20 pb2 i/o tc (2) sdadc1_ain4p, sdadc2_ain6p 38 m7 pe7 i/o tc (2) (1) sdadc1_ain3p, sdadc1_ain4m, sdadc2_ain5p, sdadc2_ain6m 39 l7 29 21 pe8 i/o tc (2) sdadc1_ain8p, sdadc2_ain8p 40 m8 30 22 pe9 i/o tc (2) sdadc1_ain7p, sdadc1_ain8m, sdadc2_ain7p, sdadc2_ain8m 41 l8 pe10 i/o tc (2) (1) sdadc1_ain2p 42 m9 pe11 i/o tc (2) (1) sdadc1_ain1p, sdadc1_ain2m, sdadc2_ain4p table 11. stm32f37x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions stm32f37x pinouts and pin description doc id 022691 rev 3 35/128 43 l9 pe12 i/o tc (2) (1) sdadc1_ain0p, sdadc2_ain3p, sdadc2_ain4m 44 m10 pe13 i/o tc (2) (1) sdadc1_ain0m , sdadc2_ain2p 45 m11 pe14 i/o tc (2) (1) sdadc2_ain1p, sdadc2_ain2m 46 m12 pe15 i/o tc (2) (1) usart3_rx sdadc2_ain0p 47 l10 pb10 i/o tc (2) (1) spi2_sck/i2s2_ck, usart3_tx, cec, tsc_sync, tim2_ch3 sdadc2_ain0m 48 l11 vrefsd- s (1) external reference voltage for sdadc1, sdadc2, sdadc3 (negative input) 49 f12 vsssd s (1) sdadc1, sdadc2, sdadc3 ground 31 23 vsssd/ vrefsd- s sdadc1, sdadc2, sdadc3 ground / external reference voltage for sdadc1, sdadc2, sdadc3 (negative input) 50 g12 vddsd12 s (1) sdadc1 and sdadc2 power supply 32 24 vddsd s sdadc1, sdadc2, sdadc3 power supply 51 l12 vddsd3 s (1) sdadc3 power supply 52 k12 33 25 vrefsd+ s external reference voltage for sdadc1, sdadc2, sdadc3 (positive input) 53 k11 34 26 pb14 i/o tc (3) spi2_miso/i2s2_mck, usart3_rts, tim15_ch1, tim12_ch1, tsc_g6_io1 sdadc3_ain8p 54 k10 35 27 pb15 i/o tc (3) spi2_mosi/i2s2_sd, tim15_ch1n, tim15_ch2, tim12_ch2, tsc_g6_io2 sdadc3_ain7p, sdadc3_ain8m, rtc_refclkin 55 k9 36 28 pd8 i/o tc (3) spi2_sck/i2s2_ck, usart3_tx, tsc_g6_io3 sdadc3_ain6p 56 k8 pd9 i/o tc (3) (1) usart3_rx, tsc_g6_io4 sdadc3_ain5p, sdadc3_ain6m 57 j12 pd10 i/o tc (3) (1) usart3_ck sdadc3_ain4p 58 j11 pd11 i/o tc (3) (1) usart3_cts sdadc3_ain3p, sdadc3_ain4m 59 j10 pd12 i/o tc (3) (1) usart3_rts, tim4_ch1, tsc_g8_io1 sdadc3_ain2p table 11. stm32f37x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions pinouts and pin description stm32f37x 36/128 doc id 022691 rev 3 60 h12 pd13 i/o tc (3) (1) tim4_ch2, tsc_g8_io2 sdadc3_ain1p, sdadc3_ain2m 61 h11 pd14 i/o tc (3) (1) tim4_ch3, tsc_g8_io3 sdadc3_ain0p 62 h10 pd15 i/o tc (3) (1) tim4_ch4, tsc_g8_io4 sdadc3_ain0m 63 e12 37 pc6 i/o ft (1) tim3_ch1, spi1_nss/i2s1_ws 64 e11 38 pc7 i/o ft (1) tim3_ch2, spi1_sck/i2s1_ck, 65 e10 39 pc8 i/o ft (1) spi1_miso/i2s1_mck, tim3_ch3 66 d12 40 pc9 i/o ft (1) spi1_mosi/i2s1_sd, tim3_ch4 67 d11 41 29 pa8 i/o ft spi2_sck/i2s2_ck, i2c2_smba, usart1_ck, tim4_etr, tim5_ch1_etr, mco 68 d10 42 30 pa9 i/o ftf spi2_miso/i2s2_mck, i2c2_scl, usart1_tx, tim2_ch3, tim15_bkin, tim13_ch1, tsc_g4_io1 69 c12 43 31 pa10 i/o ftf spi2_mosi/i2s2_sd, i2c2_sda, usart1_rx, tim2_ch4, tim17_bkin, tim14_ch1, tsc_g4_io2 70 b12 44 32 pa11 i/o ft spi2_nss/i2s2_ws, spi1_nss/i2s1_ws, usart1_cts, can_rx, tim4_ch1, usb_dm, tim5_ch2, comp1_out 71 a12 45 33 pa12 i/o ft spi1_sck/i2s1_ck, usart1_rts, can_tx, usb_dp, tim16_ch1, tim4_ch2, tim5_ch3, comp2_out 72 a11 46 34 pa13 i/o ft spi1_miso/i2s1_mck, usart3_cts, ir_out, tim16_ch1n, tim4_ch3, tim5_ch4, tsc_g4_io3, swdio-jtms table 11. stm32f37x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions stm32f37x pinouts and pin description doc id 022691 rev 3 37/128 73 c11 47 35 pf6 i/o ftf spi1_mosi/i2s1_sd, usart3_rts, tim4_ch4, i2c2_scl 74 f11 vss_3 s (1) ground 75 g11 vdd_3 s (1) digital power supply 48 36 pf7 i/o ftf i2c2_sda, usart2_ck 76 a10 49 37 pa14 i/o ftf i2c1_sda, tim12_ch1, tsc_g4_io4, swclk-jtck 77 a9 50 38 pa15 i/o ftf spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, i2c1_scl, tim2_ch1_etr, tim12_ch2, tsc_sync, jtdi 78 b11 51 pc10 i/o ft (1) spi3_sck/i2s3_ck, usart3_tx, tim19_ch1 79 c10 52 pc11 i/o ft (1) spi3_miso/i2s3_mck, usart3_rx, tim19_ch2 80 b10 53 pc12 i/o ft (1) spi3_mosi/i2s3_sd, usart3_ck, tim19_ch3 81 c9 pd0 i/o ft (1) can_rx, tim19_ch4 82 b9 pd1 i/o ft (1) can_tx, tim19_etr 83 c8 54 pd2 i/o ft (1) tim3_etr 84 b8 pd3 i/o ft (1) spi2_miso/i2s2_mck, usart2_cts 85 b7 pd4 i/o ft (1) spi2_mosi/i2s2_sd, usart2_rts 86 a6 pd5 i/o ft (1) usart2_tx 87 b6 pd6 i/o ft (1) spi2_nss/i2s2_ws, usart2_rx 88 a5 pd7 i/o ft (1) spi2_sck/i2s2_ck, usart2_ck 89 a8 55 39 pb3 i/o ft spi1_sck/i2s1_ck, spi3_sck/i2s3_ck, usart2_tx, tim2_ch2, tim3_etr, tim4_etr, tim13_ch1, tsc_g5_io1, jtdo-traceswo table 11. stm32f37x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions pinouts and pin description stm32f37x 38/128 doc id 022691 rev 3 90 a7 56 40 pb4 i/o ft spi1_miso/i2s1_mck, spi3_miso/i2s3_mck, usart2_rx, tim16_ch1, tim3_ch1, tim17_bkin, tim15_ch1n, tsc_g5_io2, jntrst 91 c5 57 41 pb5 i/o ft spi1_mosi/i2s1_sd, spi3_mosi/i2s3_sd, i2c1_smbal, usart2_ck, tim16_bkin, tim3_ch2, tim17_ch1, tim19_etr 92 b5 58 42 pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n, tim3_ch3, tim4_ch1, tim19_ch1, tim15_ch1, tsc_g5_io3 93 b4 59 43 pb7 i/o ftf i2c1_sda, usart1_rx, tim17_ch1n, tim3_ch4, tim4_ch2, tim19_ch2, tim15_ch2, tsc_g5_io4 94 a4 60 44 boot0 i b boot memory selection 95 a3 61 45 pb8 i/o ftf spi2_sck/i2s2_ck, i2c1_scl, usart3_tx, can_rx, cec, tim16_ch1, tim4_ch3, tim19_ch3, comp1_out, tsc_sync 96 b3 62 46 pb9 i/o ftf spi2_nss/i2s2_ws, i2c1_sda, usart3_rx, can_tx, ir_out, tim17_ch1, tim4_ch4, tim19_ch4, comp2_out 97 c3 pe0 i/o ft (1) usart1_tx, tim4_etr 98 a2 pe1 i/o ft (1) usart1_rx 99 d3 63 47 vss_1 s ground 100 c4 64 48 vdd_1 s digital power supply 1. when using the small packages (48 and 64 pin packages), the gpio pi ns which are not present on these packages, must not be configured in analog mode. 2. these pins are powered by vddsd12. 3. these pins are powered by vddsd3. table 11. stm32f37x pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp100 bga100 lqfp64 lqfp48 alternate function ad ditional functions stm32f37x pinouts and pin description doc id 022691 rev 3 39/128 table 12. alternate functions for port pa pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af14 af15 pa 0 tim2_ ch1_ etr tim5_ ch1_ etr tsc_ g1_io1 usart2_cts comp1 _out tim19 _ch1 event out pa 1 tim2_ ch2 tim5_ ch2 tsc_ g1_io2 spi3_sck/ i2s3_ck usart2_rts tim15_ ch1n tim19 _ch2 event out pa 2 tim2_ ch3 tim5_ ch3 tsc_ g1_io3 spi3_miso/ i2s3_mck usart2_tx comp2 _out tim15_ ch1 tim19 _ch3 event out pa 3 tim2_ ch4 tim5_ ch4 tsc_ g1_io4 spi3_mosi /i2s3_sd usart2_rx tim15_ ch2 tim19 _ch4 event out pa 4 tim3_ ch2 tsc_ g2_io1 spi1_nss/ i2s1_ws spi3_nss/ i2s3_ws usart2_ck tim12 _ch1 event out pa 5 tim2_ ch1_ etr tsc_ g2_io2 spi1_sck/ i2s1_ck cec tim14_ ch1 tim12 _ch2 event out pa 6 tim16_ ch1 tim3_ ch1 tsc_ g2_io3 spi1_miso /i2s1_mck comp1 _out tim13_ ch1 event out pa 7 tim17_ ch1 tim3_ ch2 tsc_ g2_io4 spi1_mosi /i2s1_sd comp2 _out tim14_ ch1 event out pa 8 m c o tim5_ ch1_ etr i2c2_ smba spi2_sck/ i2s2_ck usart1_ck tim4_ etr event out pa 9 tim13 _ch1 tsc_ g4_io1 i2c2_ scl spi2_miso /i2s2_mck usart1_tx tim15_ bkin tim2_ ch3 event out pa 1 0 tim17_ bkin tsc_ g4_io2 i2c2_ sda spi2_mosi /i2s2_sd usart1_rx tim14_ ch1 tim2_ ch4 event out pa 1 1 tim5_ ch2 spi2_nss/ i2s2_ws spi1_nss/ i2s1_ws usart1_cts comp1 _out can_ rx tim4_ ch1 usb_ dm event out pa 1 2 tim16_ ch1 tim5_ ch3 spi1_sck/ i2s1_ck usart1_rts comp2 _out can_tx tim4_ ch2 usb_ dp event out pinouts and pin description stm32f37x 40/128 doc id 022691 rev 3 pa 1 3 jtms- swdio tim16_ ch1n tim5_ ch4 tsc_ g4_io3 ir-out spi1_miso /i2s1_mck usart3_cts tim4_ ch3 event out pa 1 4 jtck- swclk tsc_ g4_io4 i2c1_ sda tim12 _ch1 event out pa 1 5 j t d i tim2_ ch1_etr tsc_ sync i2c1_ scl spi1_nss/ i2s1_ws spi3_nss/ i2s3_ws tim12 _ch2 event out table 12. alternate functions for port pa (continued) pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af14 af15 stm32f37x pinouts and pin description doc id 022691 rev 3 41/128 table 13. alternate functions for port pb pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af15 pb0 tim3_ch3 tsc_ g3_io3 spi_mosi/ i2s1_sd tim3_ ch2 eventout pb1 tim3_ch4 tsc_ g3_io4 eventout pb2 eventout pb3 jtdo/ traceswo tim2_ ch2 tim4_etr tsc_ g5_io1 spi1_sck/ i2s1_ck spi3_sck/ i2s3_ck usart2_tx tim13_ ch1 tim3_ etr eventout pb4 jtrst tim16_ ch1 tim3_ch1 tsc_ g5_io2 spi1_miso /i2s1_mck spi3_miso/ i2s3_mck usart2_rx tim15_ ch1n tim17 _bkin eventout pb5 tim16_ bkin tim3_ch2 i2c1_ smba spi1_mosi /i2s1_sd spi3_mosi /i2s3_sd usart2_ck tim17 _ch1 tim19 _etr eventout pb6 tim16_ ch1n tim4_ch1 tsc_ g5_io3 i2c1_ scl usart1_tx tim15_ ch1 tim3_ ch3 tim19 _ch1 eventout pb7 tim17_ ch1n tim4_ch2 tsc_ g5_io4 i2c1_ sda usart1_rx tim15_ ch2 tim3_ ch4 tim19 _ch2 eventout pb8 tim16_ ch1 tim4_ch3 tsc_ sync i2c1_ scl spi2_sck/ i2s2_ck cec usart3_tx comp1 _out can_ rx tim19 _ch3 eventout pb9 tim17_ ch1 tim4_ch4 i2c1_ sda spi2_nss/ i2s2_ws ir-out usart3_rx comp2 _out can_ tx tim19 _ch4 eventout pb10 tim2_ ch3 tsc_ synch spi2_sck/ i2s2_ck cec usart3_tx eventout pb14 tim15_ ch1 tsc_ g6_io1 spi2_miso /i2s2_mck usart3_rts tim12_ ch1 eventout pb15 tim15_ ch2 tim15_ ch1n tsc_ g6_io2 spi2_mosi /i2s2_sd tim12_ ch2 eventout pinouts and pin description stm32f37x 42/128 doc id 022691 rev 3 table 14. alternate functions for port pc pin name af0 af1 af2 af3 af4 af5 af6 af7 pc0 eventout tim5_ch1_etr pc1 eventout tim5_ch2 pc2 eventout tim5_ch3 spi2_miso/i2s2_mck pc3 eventout tim5_ch4 spi2_mosi/i2s2_sd pc4 eventout tim13_ch1 tsc_g3_io1 usart1_tx pc5 eventout tsc_g3_io2 usart1_rx pc6 eventout tim3_ch1 spi1_nss/i2s1_ws pc7 eventout tim3_ch2 spi1_sck/i2s1_ck pc8 eventout tim3_ch3 spi1_miso/i2s1_mck pc9 eventout tim3_ch4 spi1_mosi/i2s1_sd pc10 eventout tim19_ch1 spi3_sck/i2s3_ck usart3_tx pc11 eventout tim19_ch2 spi3_miso/i2s3_mck usart3_rx pc12 eventout tim19_ch3 spi3_mosi/i2s3_sd usart3_ck pc13 pc14 pc15 stm32f37x pinouts and pin description doc id 022691 rev 3 43/128 table 15. alternate functions for port pd pin name af0 af1 af2 af3 af4 af5 af6 af7 pd0 eventout tim19_ch4 can_rx pd1 eventout tim19_etr can_tx pd2 eventout tim3_etr pd3 eventout spi2_miso/i2s2_mck usart2_cts pd4 eventout spi2_mosi/i2s2_sd usart2_rts pd5 eventout usart2_tx pd6 eventout spi2_nss/i2s2_ws usart2_rx pd7 eventout spi2_sck/i2s2_ck usart2_ck pd8 eventout tsc_g6_io3 spi2_sck/i2s2_ck usart3_tx pd9 eventout tsc_g6_io4 usart3_rx pd10 eventout usart3_ck pd11 eventout usart3_cts pd12 eventout tim4_ch1 tsc_g8_io1 usart3_rts pd13 eventout tim4_ch2 tsc_g8_io2 pd14 eventout tim4_ch3 tsc_g8_io3 pd15 eventout tim4_ch4 tsc_g8_io4 pinouts and pin description stm32f37x 44/128 doc id 022691 rev 3 table 16. alternate functions for port pe pin name af0 af1 af2 af3 af4 af5 af6 af7 pe0 eventout tim4_etr usart1_tx pe1 eventout usart1_rx pe2 traceclk eventout tsc_g7_io1 pe3 traced0 eventout tsc_g7_io2 pe4 traced1 eventout tsc_g7_io3 pe5 traced2 eventout tsc_g7_io4 pe6 traced3 eventout pe7 eventout pe8 eventout pe9 eventout pe10 eventout pe11 eventout pe12 eventout pe13 eventout pe14 eventout pe15 eventout usart3_rx stm32f37x pinouts and pin description doc id 022691 rev 3 45/128 table 17. alternate functions for port pf pin name af0 af1 af2 af3 af4 af5 af6 af7 pf0 i2c2_sda pf1 i2c2_scl pf2 eventout i2c2_smba pf4 eventout pf6 eventout tim4_ch4 i2c2_scl spi1_mosi/i2s1_sd usart3_rts pf7 eventout i2c2_sda usart2_ck pf9 eventout tim14_ch1 pf10 eventout memory mapping stm32f37x 46/128 doc id 022691 rev 3 5 memory mapping figure 6. stm32f37x memory map 0xffff ffff 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0 1 2 3 4 5 6 7 cortex-m4f internal peripherals peripherals sram code option bytes system memory flash memory flash, system memory or sram, depending on boot configuration ahb2 ahb1 apb2 apb1 0x4800 17ff 0x4800 0000 0x4002 43ff 0x4002 0000 0x4001 6c00 0x4001 0000 0x4000 a000 0x4000 0000 0x1fff ffff 0x1fff f800 0x1fff d800 0x0804 0000 0x0800 0000 0x0004 0000 0x0000 0000 reserved ms30360v1 reserved reserved reserved reserved reserved stm32f37x memory mapping doc id 022691 rev 3 47/128 table 18. stm32f37x peripheral register boundary addresses bus boundary address size peripheral ahb2 0x4800 1400 - 0x4800 17ff 1kb gpiof 0x4800 1000 - 0x4800 13ff 1kb gpioe 0x4800 0c00 - 0x4800 0fff 1kb gpiod 0x4800 0800 - 0x4800 0bff 1kb gpioc 0x4800 0400 - 0x4800 07ff 1kb gpiob 0x4800 0000 - 0x4800 03ff 1kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1 kb tsc 0x4002 3400 - 0x4002 3fff 3 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash memory interface 0x4002 1400 - 0x4002 1fff 3kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0800- 0x4002 0fff 2kb reserved 0x4002 0400 - 0x4002 07ff 1 kb dma2 0x4002 0000 - 0x4002 03ff 1 kb dma1 0x4001 6c00 - 0x4001 ffff 37 kb reserved memory mapping stm32f37x 48/128 doc id 022691 rev 3 apb2 0x4001 6800 - 0x4001 6bff 1 kb sdadc3 0x4001 6400 - 0x4001 67ff 1 kb sdadc2 0x4001 6000 - 0x4001 63ff 1 kb sdadc1 0x4001 5c00 - 0x4001 5fff 1 kb tim19 0x4001 4c00 - 0x4001 5bff 4kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 0x4001 3c00 - 0x4001 3fff 1kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1/i2s1 0x4001 2800 - 0x4001 2fff 1kb reserved 0x4001 2400 - 0x4001 27ff 1 kb adc 0x4001 0800 - 0x4001 23ff 7kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0000 - 0x4001 03ff 1 kb syscfg 0x4000 4000 - 0x4000 ffff 24 kb reserved apb1 0x4000 9c00 ? 0x4000 9fff 1 kb tim18 0x4000 9800 - 0x4000 9bff 1 kb dac2 0x4000 7c00 - 0x4000 97ff 8kb reserved 0x4000 7800 - 0x4000 7bff 1 kb cec 0x4000 7400 - 0x4000 77ff 1 kb dac1 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6800 - 0x4000 6fff 2kb reserved 0x4000 6400 - 0x4000 67ff 1 kb can 0x4000 6000 - 0x4000 63ff 1 kb usb packet sram 0x4000 5c00 - 0x4000 5fff 1 kb usb fs table 18. stm32f37x peripheral register boundary addresses (continued) bus boundary address size peripheral stm32f37x memory mapping doc id 022691 rev 3 49/128 apb1 0x4000 5800 - 0x4000 5bff 1 kb i2c2 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 4c00 - 0x4000 53ff 2kb reserved 0x4000 4800 - 0x4000 4bff 1 kb usart3 0x4000 4400 - 0x4000 47ff 1 kb usart2 0x4000 4000 - 0x4000 43ff 1kb reserved 0x4000 3c00 - 0x4000 3fff 1 kb spi3/i2s3 0x4000 3800 - 0x4000 3bff 1 kb spi2/i2s2 0x4000 3400 - 0x4000 37ff 1kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1kb reserved 0x4000 2000 - 0x4000 23ff 1 kb tim14 0x4000 1c00 - 0x4000 1fff 1 kb tim13 0x4000 1800 - 0x4000 1bff 1 kb tim12 0x4000 1400 - 0x4000 17ff 1 kb tim7 0x4000 1000 - 0x4000 13ff 1 kb tim6 0x4000 0c00 - 0x4000 0fff 1 kb tim5 0x4000 0800 - 0x4000 0bff 1 kb tim4 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb tim2 table 18. stm32f37x peripheral register boundary addresses (continued) bus boundary address size peripheral electrical characteristics stm32f37x 50/128 doc id 022691 rev 3 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = v ddsdx = 3.3 v. they are given only as design guidelines and are not tested. typical adc and sdadc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 7 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 8 . figure 7. pin loading condition s figure 8. pin input voltage - 3 6 c = 50 pf - # 5 p i n - 3 6 - # 5 p i n 6 ) . stm32f37x electrical characteristics doc id 022691 rev 3 51/128 6.1.6 power supply scheme figure 9. power supply scheme 1. dotted lines represent the inter nal connections on low pin count pa ckages, joining the dedicated supply pins. ms19232v3 analog: rcs, pll, comp, ... po wer swi tch v bat gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (lse,rtc, backup registers) wakeup logic 2 100 nf + 1 4.7 f 1. 65 - 3.6 v regulator v dda v ssa adc/ dac level shifter io logic v dd 10 nf + 1 f v dda v ref+ v ref- v dd v ss 3 2 sigma delta adcs 10 nf + 1 f vddsd12 vddsd12 vddsd3 vddsd3 vsssd 10 nf + 1 f vrefsd+ vrefsd- 10 nf + 1 f vrefsd+ gp i/o s out in level shifter io logic gp i/o s out in level shifter io logic 10 nf + 1 f v ref ref+ v 1.8 v @v dd @vddsd3 @vddsd12 electrical characteristics stm32f37x 52/128 doc id 022691 rev 3 caution: each power supply pair (v dd /v ss , v dda /v ssa etc..) must be decoupled with filtering ceramic capacitors as shown above. these capac itors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 6.1.7 current con sumption measurement figure 10. current consumption measurement scheme - 3 6 6 " ! 4 6 $ $ 6 $ $ ! ) $ $ ? 6 " ! 4 ) $ $ ) $ $ ! 6 $ $ 3 $ ) $ $ 3 $ ) $ $ 3 $ 6 $ $ 3 $ stm32f37x electrical characteristics doc id 022691 rev 3 53/128 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 19: voltage characteristics , table 20: current characteristics , and table 21: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. all main power (vdd, vddsd12, vddsd3 and vdda) and groun d (vss, vsssd, and vssa) pins must always be connected to the ex ternal power supply, in the permitted range. the following relationship must be respected between v dda and v dd : v dda must power on before or at the same time as v dd in the power up sequence. v dda must be greater than or equal to v dd . the following relationship must be respected between v dda and v ddsd12 : v dda must power on before or at the same time as v ddsd12 or v ddsd3 in the power up sequence. v dda must be greater than or equal to v ddsd12 or v ddsd3 . the following relationship must be respected between v ddsd12 and v ddsd3 : v ddsd3 must power on before or at the same time as v ddsd12 in the power up sequence. after power up (v ddsd12 > vrefint = 1.2 v) v ddsd3 can be higher or lower than v ddsd12 . the following relationship must be respected between v refsd+ and v ddsd12 , v ddsd3 : v refsd+ must be lower than v ddsd3 . table 19. voltage characteristics (1) symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda, v ddsdx , v bat and v dd ) ?? 0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda 0.4 v ddsdx ? v dda allowed voltage difference for v ddsdx > v dda 0.4 v refsd+ ? v ddsd3 allowed voltage difference for v refsd+ > v ddsd3 0.4 v ref+ ? v dda allowed voltage difference for v ref+ > v dda 0.4 v in (2) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 input voltage on tta pins v ss ? 0.3 4.0 input voltage on tc pins on sdadcx channels inputs (3) v ss ?? 0.3 4.0 input voltage on any other pin v ss ?? 0.3 4.0 |v ssx ?? v ss | variations between all the different ground pins 50 mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. v in maximum must always be respected. refer to table 20: current characteristics for the maximum allowed injected current values. 3. vddsd12 is the external power supply for pb2, pb10, and pe7 to pe15 i/o pins (i/o ground pi n is internally connected to v ss ). vddsd3 is the external power supply for pb14 to pb 15 and pd8 to pd15 i/o pins (i /o ground pin is internally connected to v ss ). electrical characteristics stm32f37x 54/128 doc id 022691 rev 3 depending on the sdadcx operation mode, there can be more constraints between v refsd+ , v ddsd12 and v ddsd3 which are described in reference manual rm0313. table 20. current characteristics symbol ratings max. unit i vdd( ?? total current into sum of all vdd_x and vddsdx power lines (source) (1) 160 ma i vss( ?? total current out of sum of all vss_x and vsssd ground lines (sink) (1) -160 i vdd(pin) maximum current into each vdd_ x or vddsdx power pin (source) (1) 100 i vss(pin) maximum current out of each vss_x or vsssd ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin - 25 ? i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 i inj(pin) injected current on ft, ftf and b pins (3) -5/+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 ? i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. vddsd12 is the external power suppl y for pb2, pb10, and pe7 to pe15 i/o pi ns (the i/o pin ground is internally connected to v ss ). vddsd3 is the external powe r supply for pb14 to pb15 and pd8 to pd15 i/o pins (the i/o pin ground is internally connected to v ss ). v dd (vdd_x) is the external power supply for a ll remaining i/o pins (the i/o pin ground is internally connected to v ss ). 2. this current consumption must be correc tly distributed over all i/os and control pi ns. the total output current must not be sunk/sourced between two consecutiv e power supply pins referring to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in >v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 19: voltage characteristics for the maximum allowed input voltage values. 5. a positive injection is induced by v in >v dda while a negative injection is induced by v in < v ss . i inj (pin) must never be exceeded. refer also to table 19: voltage characteristics for the maximum allowed input voltage values. negative injection disturbs the analog performanc e of the device. see note (2) below table 62 . 6. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 21. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c stm32f37x electrical characteristics doc id 022691 rev 3 55/128 6.3 operating conditions 6.3.1 general operating conditions table 22. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage must have a potential equal to or lower than v dda 23.6v v dda (1) analog operating voltage (adc and dac used) must have a potential equal to or higher than v dd 2.4 3.6 v analog operating voltage (adc and dac not used) 23.6 v ddsd12 vddsd12 operating voltage (sdadc used) must have a potential equal to or lower than v dda 2.2 3.6 v vddsd12 operating voltage (sdadc not used) 2.0 3.6 v ddsd3 vddsd3 operating voltage (sdadc used) must have a potential equal to or lower than v dda 2.2 3.6 v vddsd3 operating voltage (sdadc not used) 2.0 3.6 v bat backup operating voltage 1.65 3.6 v v in input voltage on ft and ftf pins (2) - 0.3 5.5 v input voltage on tta pins - 0.3 v dda + 0.3 input voltage on tc pins on sdadcx channels inputs (3) - 0.3 v ddsdx + 0.3 input voltage on boot0 pin 0 5.5 input voltage on any other pin - 0.3 v dd + 0.3 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (4) lqfp100 434 mw lqfp64 444 lqfp48 364 bga100 338 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (5) ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (5) ?40 125 electrical characteristics stm32f37x 56/128 doc id 022691 rev 3 6.3.2 operating conditions at power-up / power-down the parameters given in ta bl e 2 3 are derived from tests performed under the ambient temperature condition summarized in ta b l e 2 2 . t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 1. when the adc is used, refer to table 60: adc characteristics . 2. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pul l-down resistors must be disabled. 3. vddsd12 is the external power supply for pb2, pb 10, and pe7 to pe15 i/o pins (the i/o pin ground is internally connected to vss). vddsd3 is the external power supply for pb14 to pb15 and pd8 to pd15 i/o pins (the i/o pin ground is internally connected to vss). 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see table 21: thermal characteristics ). 5. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see table 21: thermal characteristics ). table 22. general operating conditions (continued) symbol parameter conditions min max unit table 23. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate 0 ? v dda fall time rate 20 ? stm32f37x electrical characteristics doc id 022691 rev 3 57/128 6.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 2 4 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 2 2 . table 24. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd , v dda and v ddsd12 (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (3) pdr hysteresis 40 mv t rsttempo (3) 3. guaranteed by design, not tested in production. por reset temporization 1.5 2.5 4.5 ms table 25. programmable voltage detector characteristics symbol parameter conditions min (1) 1. data based on characterization results only, not tested in production. typ max (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 v falling edge 2.09 2.18 2.27 v v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 v falling edge 2.18 2.28 2.38 v v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 v falling edge 2.28 2.38 2.48 v v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 v falling edge 2.37 2.48 2.59 v v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 v falling edge 2.47 2.58 2.69 v v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 v falling edge 2.56 2.68 2.8 v v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 v falling edge 2.66 2.78 2.9 v v pvdhyst (2) 2. guaranteed by design, not tested in production. pvd hysteresis 100 mv idd(pvd) (2) pvd current consumption 0.15 0.26 a electrical characteristics stm32f37x 58/128 doc id 022691 rev 3 6.3.4 embedded reference voltage the parameters given in ta bl e 2 7 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 2 2 . table 26. embedded internal reference voltage calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb table 27. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.21 1.26 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) t s_vrefint (2) adc sampling time when reading the internal reference voltage 17.1 - - s v refint_s (3) internal reference voltage spread over the temperature range v dd = 3 v 10 mv - 10 mv t coeff (3) temperature coefficient - 100 ppm/c t start (3) startup time - 10 s 1. data based on characterization results, not tested in production. 2. shortest sampling time can be determined in the application by multiple iterations. 3. guaranteed by design, not tested in production. stm32f37x electrical characteristics doc id 022691 rev 3 59/128 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 10: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f apb1 = f ahb /2 , f apb2 = f ahb when f hclk > 8 mhz pll is on and pll inputs is equal to hsi/2 = 4 mhz (if internal clock is used) or hse = 8 mhz (if hse bypass mode is used) the parameters given in ta bl e 2 8 to ta bl e 3 4 are derived from tests performed under ambient temperature and supply voltage conditions summarized in ta b l e 2 2 . table 28. typical and maximum current consumption from v dd supply at v dd = 3.6 v symbol parameter conditions f hclk all peripherals enabled a ll peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, code executing from flash hse bypass, pll on 72 mhz 63.1 70.7 71.5 73. 4 29.2 31.1 31.7 34.2 ma 64 mhz 56.3 63.3 64.1 64. 9 26.1 27.8 28.4 30.4 48 mhz 42.5 48.5 48.0 50. 1 19.9 22.6 21.9 23.1 32 mhz 28.8 31.4 32.2 34. 3 13.1 16.1 14.9 16.2 24 mhz 21.9 24.4 24.4 25. 8 10.1 10.9 11.9 12.4 hse bypass, pll off 8 mhz 7.3 8.0 9.3 9.3 3.7 4.1 4.4 5.0 1 mhz 1.1 1.5 1.8 2.3 0.8 1.1 1.4 1.9 hsi clock, pll on 64 mhz 51.7 57.7 58.0 60. 4 25.8 27.6 28.1 30.1 48 mhz 38.6 45.9 43.5 46. 9 19.8 21.9 21.7 22.8 32 mhz 26.4 31.1 29.7 31. 9 13.1 15.7 14.8 16.2 24 mhz 20.3 22.6 22.6 23.7 6.9 7.5 8.1 8.8 hsi clock, pll off 8 mhz 7.0 7.6 8.8 8.8 3.7 4.1 4.4 5.0 electrical characteristics stm32f37x 60/128 doc id 022691 rev 3 i dd supply current in run mode, code executing from ram hse bypass, pll on 72 mhz 63.6 (2) 70.7 (2) 75.7 (2) 72.3 (2) 30.0 (2) 31.9 (2) 32.6 (2) 33.8 (2) ma 64 mhz 56.7 62.5 67.1 64. 0 26.7 28.6 29.3 30.0 48 mhz 42.0 50.5 47.4 50. 1 20.2 21.5 22.1 22.7 32 mhz 28.3 32.1 31.8 33. 7 13.4 14.6 14.8 15.7 24 mhz 21.1 25.0 24.2 25. 9 10.0 11.3 11.2 12.6 hse bypass, pll off 8 mhz 6.9 7.4 8.3 8.7 3.4 3.7 4.1 4.8 1 mhz 0.8 1.2 1.5 2.0 0.4 0.6 1.0 1.5 hsi clock, pll on 64 mhz 51.9 59.5 59.4 58. 6 26.4 28.1 28.7 29.5 48 mhz 38.1 44.7 43.8 45. 4 20.0 21.3 21.9 22.3 32 mhz 25.9 31.2 29.4 30. 5 13.2 14.3 14.6 15.5 24 mhz 19.6 22.7 22.6 23.2 6.5 7.0 7.9 8.2 hsi clock, pll off 8 mhz 6.6 7.1 8.0 8.4 3.3 3.7 4.0 4.7 supply current in sleep mode, code executing from flash or ram hse bypass, pll on 72 mhz 43.2 46.9 48.7 52.5 6.7 7.2 7.6 8.3 64 mhz 38.5 41.6 43.7 46.6 5.9 6.5 6.8 7.5 48 mhz 29.1 31.3 32.5 34.1 4.5 4.9 5.3 5.9 32 mhz 19.4 21.1 24.6 23.0 3.0 3.4 3.8 4.4 24 mhz 14.7 16.1 18.5 17.6 2.4 2.6 3.0 3.6 hse bypass, pll off 8 mhz 4.9 5.3 6.1 6.6 0.8 1.0 1.4 1.9 1 mhz 0.6 0.9 1.3 1.8 0.1 0.3 0.6 1.2 hsi clock, pll on 64 mhz 34.5 37.1 39.6 42.0 5.6 6.1 6.5 7.1 48 mhz 26.1 28.0 29.0 30.7 4.2 4.6 5.0 5.6 32 mhz 17.4 19.1 21.1 20.8 2.9 3.2 3.6 4.2 24 mhz 13.3 14.6 16.1 16.0 1.5 1.8 2.2 2.6 hsi clock, pll off 8 mhz 4.5 4.9 5.5 6.1 0.7 0.9 1.3 1.8 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and test ed in production with c ode executing from ram. table 28. typical and maximum current consumption from v dd supply at v dd = 3.6 v symbol parameter conditions f hclk all peripherals enabled a ll peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c stm32f37x electrical characteristics doc id 022691 rev 3 61/128 note: v dda monitoring is off and v ddsd12 monitoring is off table 29. typical and maximum current consumption from v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run or sleep mode, code executing from flash or ram hse bypass, pll on 72 mhz 228 261 274 280 249 288 304 311 a 64 mhz 201 235 247 251 220 257 269 275 48 mhz 152 182 190 195 164 196 208 212 32 mhz 104 132 137 141 112 141 147 150 24 mhz 81 108 112 111 87 115 119 119 hse bypass, pll off 8 mhz 2 4 4 5 3 5 5 6 1 mhz 2 4 5 5 3 5 5 6 hsi clock, pll on 64 mhz 270 307 320 326 298 337 353 361 48 mhz 220 254 264 269 243 276 292 297 32 mhz 172 203 211 214 191 222 232 235 24 mhz 151 181 185 189 166 194 201 204 hsi clock, pll off 8 mhz 70 85 87 87 81 93 96 98 1. current consumption from the v dda supply is independent of whether the perip herals are on or off. furthermore when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production unless otherwise specified. table 30. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ@v dd (v dd =v dda )max unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulators in run mode, all oscillators off 19.33 19.58 19.68 19.73 19.76 19.84 46.5 480 1019 a regulators in low-power mode, all oscillators off 7.72 7.88 8.01 8.13 8.25 8.27 31.8 451.4 966.0 supply current in standby mode lsi on and iwdg on 0.78 0.95 1.07 1.21 1.32 1.45 lsi off and iwdg off 0.61 0.72 0.81 0.90 0.98 1.08 2.7 3.5 5.3 electrical characteristics stm32f37x 62/128 doc id 022691 rev 3 table 31. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ@v dd (v dd =v dda )max (1) unit 2.0 v2.4 v2.7 v3.0 v3.3 v3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode v dda and v ddsd12 regulator in run mode, all oscillators off 1.99 2.07 2.19 2.33 2.46 2.64 10.8 11.8 12.4 a regulator in low-power mode, all oscillators off 1.99 2.07 2.18 2.32 2.47 2.63 10.6 11.5 12.5 supply current in standby mode lsi on and iwdg on 2.44 2.53 2.7 2.89 3.09 3.33 lsi off and iwdg off 1.87 1.94 2.06 2.19 2.35 2.51 4.1 4.5 4.8 iddamon supply current for v dda and v ddsd12 monitoring - 0.95 1.02 1.12 1.2 1.27 1.4 1. data based on characterization results and tested in production. 2. to obtain data with monitoring off is nec essary to substract the iddamon current. table 32. typical and maximum current consumption from v bat supply (1) symbol parameter conditions typ @ v bat max (2) unit = 1.65 v = 1.8 v = 2.0 v = 2.4 v = 2.7 v = 3.3 v = 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd_ vbat backup domain supply current lse & rtc on; "xtal mode" lower driving capability; lsedrv[1:0] = '00' 0.50 0.52 0.55 0.63 0.70 0.87 0.95 1.1 1.6 2.2 a lse & rtc on; "xtal mode" higher driving capability; lsedrv[1:0] = '11' 0.85 0.90 0.93 1.02 1.10 1.27 1.38 1.6 2.4 3.0 1. crystal used: abracon abs07-120-32.768khz-t with 6 pf of cl for typical values. 2. data based on characterization results, not tested in production. stm32f37x electrical characteristics doc id 022691 rev 3 63/128 figure 11. typical v bat current consumption (lse and rtc on/lsedrv[1:0]='00') typical current consumption the mcu is placed under the following conditions: v dd = v dda = v ddsd12 = v ddsd3 = 3.3 v all i/o pins are in analog input configuration the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz) prefetch is on when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb pll is used for frequencies greater than 8 mhz ahb prescaler of 2, 4, 8, 16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively 0 0 .2 0 .4 0 .6 0 .8 1 1 .2 1 .4 1 .6 25c 60c 85c 105c 1.65 v 1.8 v 2 v 2.4 v 2.7 v 3 v 3.3 v 3.6 v - 3 6 ? ! ) 6 " ! 4 4 ! ? # electrical characteristics stm32f37x 64/128 doc id 022691 rev 3 table 33. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash, pll on 72 mhz 61.4 28.8 ma 64 mhz 55.4 25.9 48 mhz 42.3 20.0 32 mhz 28.7 13.8 24 mhz 21.9 10.7 16 mhz 14.8 7.4 running from hse crystal clock 8 mhz, code executing from flash, pll off 8 mhz 7.8 4.1 4 mhz 4.6 2.6 2 mhz 2.9 1.8 1 mhz 2.0 1.3 500 khz 1.5 1.1 125 khz 1.2 1.0 i dda (1)(2) supply current in run mode from v dda supply running from hse crystal clock 8 mhz, code executing from flash, pll on 72 mhz 243.3 242.4 a 64 mhz 214.3 213.3 48 mhz 159.3 158.3 32 mhz 107.7 107.3 24 mhz 82.8 82.6 16 mhz 58.4 58.2 running from hse crystal clock 8 mhz, code executing from flash, pll off 8 mhz 1.2 1.2 4 mhz 1.2 1.2 2 mhz 1.2 1.2 1 mhz 1.2 1.2 500 khz 1.2 1.2 125 khz 1.2 1.2 i sdadc12 + i sdadc3 supply currents in run mode from v ddsd12 and v ddsd3 (sdadcs are off) -2.5 1 1. v dda monitoring is off, v ddsd12 monitoring is off. 2. when peripherals are enabled, pow er consumption of the analog part of periphe rals such as adc, dacs, comparators, etc. is not included. refer to those peripheral s characteristics in the subsequent sections. stm32f37x electrical characteristics doc id 022691 rev 3 65/128 table 34. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram, pll on 72 mhz 42.8 6.9 ma 64 mhz 38.2 6.2 48 mhz 28.9 4.8 32 mhz 19.5 3.4 24 mhz 14.7 2.7 16 mhz 10.2 2.0 running from hse crystal clock 8 mhz, code executing from flash or ram, pll off 8 mhz 5.2 1.2 4 mhz 3.4 1.1 2 mhz 2.2 0.9 1 mhz 1.6 0.9 500 khz 1.4 0.8 125 khz 1.1 0.8 i dda (1) supply current in sleep mode from v dda supply running from hse crystal clock 8 mhz, code executing from flash or ram, pll on 72 mhz 242.9 241.5 a 64 mhz 213.7 212.7 48 mhz 158.8 158.0 32 mhz 107.6 107.3 24 mhz 82.7 82.6 16 mhz 58.3 58.2 running from hse crystal clock 8 mhz, code executing from flash or ram, pll off 8 mhz 1.2 1.2 4 mhz 1.2 1.2 2 mhz 1.2 1.2 1 mhz 1.2 1.2 500 khz 1.2 1.2 125 khz 1.2 1.2 1. v dda monitoring is off, v ddsd12 monitoring is off. electrical characteristics stm32f37x 66/128 doc id 022691 rev 3 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 52: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc and sdadc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. under reset conditions all i/os are configured in input floating mode - so if some inputs do not have a defined voltage level then they can generate additional consumption. this consumption is visible on v dd supply and also on v ddsdx supply because some i/os are powered from sdadcx supp ly (all i/os which have sdadc analog input functionality). i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 36: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacita nce including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c ? ? = stm32f37x electrical characteristics doc id 022691 rev 3 67/128 table 35. switching output i/o current consumption symbol parameter conditions (1) i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.77 ma 4 mhz 0.87 8 mhz 0.95 18 mhz 1.59 36 mhz 2.57 48 mhz 3.11 v dd = 3.3 v c ext = 10 pf c = c int + c ext + cs 2 mhz 0.96 4 mhz 1.0 8 mhz 1.08 18 mhz 2.17 36 mhz 3.42 48 mhz 5.50 v dd = 3.3 v c ext = 22 pf c = c int + c ext + cs 2 mhz 0.98 4 mhz 1.23 8 mhz 1.48 18 mhz 2.93 36 mhz 6.59 48 mhz 7.03 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 1.03 ma 4 mhz 1.3 8 mhz 1.81 18 mhz 3.42 36 mhz 8.27 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s 2 mhz 1.09 4 mhz 1.55 8 mhz 2.18 18 mhz 4.38 36 mhz 9.65 1. c s = 5 pf (estimated value). electrical characteristics stm32f37x 68/128 doc id 022691 rev 3 on-chip peripheral current consumption the mcu is placed under the following conditions: all i/o pins are in analog input configuration all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature at 25c and v dd = v dda = 3.3 volts table 36. peripheral current consumption peripheral typical consumption (1) unit ahb peripherals busmatrix (2) 6.9 a/mhz dma1 18.3 dma2 4.8 crc 2.6 gpioa 12.2 gpiob 11.9 gpioc 4.3 gpiod 12.0 gpioe 4.4 gpiof 3.7 tsc 5.7 apb2 peripherals apb2-bridge (3) 4.2 syscfg 2.8 adc1 17.7 spi1 12.3 usart1 22.9 tim15 15.7 tim16 12.2 tim17 12.1 tim19 18.5 sdac1 10.8 sdac2 10.5 sdac3 10.3 stm32f37x electrical characteristics doc id 022691 rev 3 69/128 apb1 peripherals a/mhz apb1-bridge (3) 6.9 tim2 47.9 tim3 36.8 tim4 36.9 tim5 45.5 tim6 8.4 tim7 8.2 tim12 21.3 tim13 14.2 tim14 14.4 tim18 10.1 wwdg 4.7 spi2 24.3 spi3 25.3 usart2 45.3 usart3 43.1 i2c1 14.0 i2c2 13.9 usb 27.9 can 38.1 dac2 7.7 pwr 5.4 dac1 14.8 cec 5.4 1. when peripherals are enabled, power consumption of the analog part of per ipherals such as adc, dacs, comparators, etc. is not included. refer to those per ipherals characteristics in the subsequent sections. 2. the busmatrix is automatically active when at least one master is on (cpu, dma1 or dma2). 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. table 36. peripheral current consumption peripheral typical consumption (1) unit electrical characteristics stm32f37x 70/128 doc id 022691 rev 3 6.3.6 wakeup time from low-power mode the wakeup times given in ta b l e 3 7 are measured from the wakeup event trigger to the first instruction executed by the cpu. the clock source used to wake up the device depends from the current operating mode: stop or sleep mode: the wakeup event is wfe wkup1 (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . 6.3.7 external cloc k source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 12 . table 37. low-power mode wakeup timings symbol parameter conditions typ @v dd = v dda max unit = 2.0 v = 2.4 v = 2.7 v = 3 v = 3.3 v t wustop wakeup from stop mode regulator in run mode 4.1 3.9 3.8 3.7 3.6 4.5 s regulator in low power mode 7.9 6.7 6.1 5.7 5.4 8.6 t wustandby wakeup from standby mode lsi and iwdg off 62.6 53.7 49.2 45.7 42.7 100 t wusleep wakeup from sleep mode after wfe instruction 6 cpu clock cycles table 38. high-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f hse_ext user external clock source frequency 1832mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hseh) t w(hsel) osc_in high or low time 15 ns t r(hse) t f(hse) osc_in rise or fall time 20 stm32f37x electrical characteristics doc id 022691 rev 3 71/128 figure 12. high-speed external clock source ac timing diagram low-speed external user clock generated from an external source in bypass mode the lse oscilla tor is switched off and the in put pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 13 . table 39. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f lse_ext user external clock source frequency 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lseh) t w(lsel) osc32_in high or low time 450 ns t r(lse) t f(lse) osc32_in rise or fall time 50 - 3 6 6 ( 3 % ( t f ( 3 % 4 ( 3 % t t r ( 3 % 6 ( 3 % , t 7 ( 3 % ( t 7 ( 3 % , electrical characteristics stm32f37x 72/128 doc id 022691 rev 3 figure 13. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are base d on design simulation results obtained with typi cal external components specified in ta b l e 4 0 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 40. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor 200 k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time 8.5 ma v dd = 3.3 v, rm= 30 ? , cl= 10 pf@8 mhz 0.4 v dd = 3.3 v, rm= 45 ? , cl= 10 pf@8 mhz 0.5 v dd = 3.3 v, rm= 30 ? , cl=5 pf@32 mhz 0.8 v dd = 3.3 v, rm= 30 ? , cl= 10 pf@32 mhz 1 v dd = 3.3 v, rm= 30 ? , cl= 20 pf@32 mhz 1.5 g m oscillator transconductance startup 10 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms - 3 6 6 , 3 % ( t f , 3 % 4 , 3 % t t r , 3 % 6 , 3 % , t 7 , 3 % ( t 7 , 3 % , stm32f37x electrical characteristics doc id 022691 rev 3 73/128 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 14 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on electing the crystal, refer to the applicatio n note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 14. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f ( 3 % # , 2 & - ( z r e s o n a t o r 2 % 8 4 # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n electrical characteristics stm32f37x 74/128 doc id 022691 rev 3 low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information given in this pa ragraph are based on de sign simulation results obtained with typica l external components specified in ta bl e 4 1 . in the application, the resonator and the load capacitors have to be placed as clos e as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the app lication note an 2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 41. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability 0.5 0.9 a lsedrv[1:0]= 01 medium low driving capability 1 lsedrv[1:0] = 10 medium high driving capability 1.3 lsedrv[1:0]=11 higher driving capability 1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5 a/v lsedrv[1:0]= 01 medium low driving capability 8 lsedrv[1:0] = 10 medium high driving capability 15 lsedrv[1:0]=11 higher driving capability 25 t su(lse) (3) startup time v dd is stabilized 2 s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enab led (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly wi th the crystal manufacturer stm32f37x electrical characteristics doc id 022691 rev 3 75/128 figure 15. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 6.3.8 internal clock source characteristics the parameters given in ta bl e 4 2 are derived from tests performed under ambient temperature and supply voltage conditions summarized in ta b l e 2 2 . the provided curves are chararacterization results, not tested in production. high-speed internal (hsi) rc oscillator - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f , 3 % # , k ( z r e s o n a t o r # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s $ r i v e p r o g r a m m a b l e a m p l i f i e r table 42. hsi oscillator characteristics (1) 1. v dda =3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz trim hsi user trimming step 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) 55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. 4.6 (3) % t a = ?10 to 85 c ?2.9 (3) 2.9 (3) % t a = 0 to 70 c % t a = 25 c ?1 1 % t su(hsi) hsi oscillator startup time 1 (3) 2 (3) s i dd(hsi) hsi oscillator power consumption 80 100 (3) a electrical characteristics stm32f37x 76/128 doc id 022691 rev 3 figure 16. hsi oscillator accuracy characterization results low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in ta bl e 4 4 are derived from tests performed under ambient temperature and supply voltage conditions summarized in ta b l e 2 2 . table 43. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 60 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (2) lsi oscillator power consumption 0.75 1.2 a - 3 6 - ! 8 - ) . 4 ! ; ? # = ! # # ( 3 ) table 44. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1 (2) 24 (2) mhz pll input clock duty cycle 40 (2) 60 (2) % f pll_out pll multiplier output clock 16 (2) 72 mhz t lock pll lock time 200 (2) s jitter cycle-to-cycle jitter 300 (2) ps stm32f37x electrical characteristics doc id 022691 rev 3 77/128 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 1. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 2. guaranteed by design, not tested in production. table 45. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ??? ?40 to +105 c 40 53.5 60 s t erase page (2 kb) erase time t a ?? ?40 to +105 c 20 40 ms t me mass erase time t a ?? ?40 to +105 c 20 40 ms i dd supply current write mode 10 ma erase mode 12 ma table 46. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. data based on characterization results, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 ye a r s 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 electrical characteristics stm32f37x 78/128 doc id 022691 rev 3 6.3.11 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 4 7 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) table 47. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp100, t a ?? +25 c, f hclk ?? 72 mhz conforms to iec 61000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp100, t a ?? +25 c, f hclk ?? 72 mhz conforms to iec 61000-4-4 4a stm32f37x electrical characteristics doc id 022691 rev 3 79/128 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sensi tivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 48. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd ?? 3.3 v, t a ?? 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz 9 dbv 30 to 130 mhz 26 130 mhz to 1 ghz 30 sae emi level 4 - table 49. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to jesd22-c101, lqfp100, lqfp64, lqfp48 and bga100 packages ii 500 t a ?? +25 c, conforming to jesd22-c101, wlcsp66 package ii 250 electrical characteristics stm32f37x 80/128 doc id 022691 rev 3 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failu re (for example reset occurrence or oscillator frequency deviation). the test results are given in ta b l e 5 1 . table 50. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a stm32f37x electrical characteristics doc id 022691 rev 3 81/128 note: 1 it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 51. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin -0 na ma injected current on pc0 pin -0 +5 injected current on tc type i/o pins on vddsd12 power domain: pb0, pb1, pb2, pe7, pe8, pe9, pe10, pe11, pe12, pe13, pe14, pe15, pb10 with induced leakage current on other pins from this group less than -50 a -5 +5 injected current on tc type i/o pins on vddsd3 power domain: pb14, pb15, pd8, pd 9, pd10, pd12, pd13, pd14, pd15 with induced leakage current on other pins from this group less than -50 a -5 +5 injected current on tta type pins: pa4, pa5, pa6 with induced leakage current on adjacent pins less than -10 a -5 +5 injected current on any other ft and ftf pins -5 na injected current on any other pins -5 +5 electrical characteristics stm32f37x 82/128 doc id 022691 rev 3 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 5 2 are derived from tests performed under the conditions summarized in ta b l e 2 2 . all i/os are cmos and ttl compliant. table 52. i/o static characteristics (1) symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3v dd +0.07 (2) v ft and ftf i/o - - 0.475v dd ?0.2 (2) boot0 - - 0.3v dd ?0.3 (2) all i/os except boot0 pin - - 0.3v dd v ih high level input voltage tc and tta i/o 0.445v dd +0.398 (2) - ft and ftf i/o 0.5v dd +0.2 (2) - boot0 0.2v dd +0.95 (2) - all i/os except boot0 pin 0.7v dd - v hys schmitt trigger hysteresis tc and tta i/o - 200 (2) - mv ft and ftf i/o - 100 (2) - boot0 - 300 (2) - i lkg input leakage current (3) tc, ft and ftf i/o tta in digital mode v ss ? v in ?? v dd -- ? 0 ? 1 a tta in digital mode v dd ?? v in ? v dda --1 tta in analog mode v ss ? v in ? v dda --0.2 ft and ftf i/o (3) v dd ? v in ? 5 v --10 r pu weak pull-up equivalent resistor (4) v in = ? v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (4) v in = ? v dd 25 40 55 c io i/o pin capacitance - 5 - pf 1. vddsd12 is the external power supply for pb2, pb10, and pe7 to pe15 i/o pins (the i/o pin ground is internally connected to vss). vddsd3 is the external power supply for pb14 to pb 15 and pd8 to pd15 i/o pins (the i/o pin ground is internally connected to vss). for those pins all v dd supply references in this table are re lated to their given vddsdx power supply. 2. data based on design simulati on only. not tested in production. 3. leakage could be higher than maximum value, if negative current is injected on adjacent pins. 4. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). stm32f37x electrical characteristics doc id 022691 rev 3 83/128 note: i/o pins are powered from v dd voltage except pins which can be used as sdadc inputs: - pb2, pb10 and pe7 to pe15 i/o pins are powered from vddsd12. - pb14 to pb15 and pd8 to pd15 i/o pins ar e powered from vddsd3. all i/o pin ground is internally connected to v ss . v dd mentioned in the ta bl e 5 2 represents power voltage for a given i/o pin (vdd or vddsd12 or vddsd3). all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 17 and figure 18 for standard i/os, and in figure 19 and figure 20 for 5 v tolerant i/os. figure 17. tc and tta i/o input characteristics - cmos port figure 18. tc and tta i/o input characteristics - ttl port ms30255v2 v dd (v) v ihmin 2.0 v ilmax 0.7 v il /v ih (v) 1.3 2.0 3.6 v ilmax = 0.3v dd +0.07 0.6 2.7 3.0 3.3 cmos standard requirements v ilmax = 0.3v dd v ihmin = 0.445v dd +0.398 area not determined tested in production tested in production based on design simulations based on design simulations cmos standard requirements v ihmin = 0.7 v dd v dd (v) v ihmin 2.0 v ilmax 0.7 v il /v ih (v) 1.3 2.0 3.6 v ilmax = 0.3v dd + 0.07 0.8 2.7 3.0 3.3 v ihmin = 0.445v dd +0.398 area not determined based on design simulations based on design simulations - 3 6 ttl standard requirements v ihmin = 2 v ttl standard requirements v ilmax = 0.8 v electrical characteristics stm32f37x 84/128 doc id 022691 rev 3 figure 19. five volt tolerant (ft and ftf) i/o input characteristics - cmos port figure 20. five volt tolerant (ft and ftf) i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 6.2 : the sum of the currents sourced by all the i/os on all vdd_x and vddsdx, plus the maximum run consumption of the mcu sourced on v dd cannot exceed the absolute maximum rating i vdd ( ?? (see ta bl e 2 0 ). the sum of the currents sunk by all the i/os on a ll vss_x and vsssd, plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss ( ?? (see ta bl e 2 0 ). v dd (v) 2.0 0.5 v il /v ih (v) 2.0 3.6 1.0 2.7 area not determined - 3 6 v ilmax = 0.475v dd -0.2 v ihmin = 0.5v dd +0.2 based on design simulations based on design simulations cmos standard requirements v ihmin = 0.7v dd cmos standard requirements v ilmax = 0.3v dd v dd (v) 2.0 0.5 v il /v ih (v) 2.0 3.6 1.0 2.7 area not determined - 3 6 v ilmax = 0.475v dd -0.2 v ihmin = 0.5v dd +0.2 based on design simulations based on design simulations ttl standard requirements v ihmin = 2 v ttl standard requirements v ilmax = 0.8 v 0.8 stm32f37x electrical characteristics doc id 022691 rev 3 85/128 output voltage levels unless otherwise specified, the parameters given in ta bl e 5 3 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . all i/os are cmos and ttl compliant (ft, tta or tc unless otherwise specified). note: i/o pins are powered from v dd voltage except pins which can be used as sdadc inputs: - pb2, pb10 and pe7 to pe15 i/o pins are powered from vddsd12. - pb14 to pb15 and pd8 to pd15 i/o pins ar e powered from vddsd3. all i/o pin ground is internally connected to v ss . v dd mentioned in the ta bl e 5 3 represents power voltage for a given i/o pin (vdd or vddsd12 or vddsd3). table 53. output voltage characteristics (1) 1. vddsd12 is the external power supply for pb2, pb 10, and pe7 to pe15 i/o pins (the i/o ground pin is internally connected to vss). vddsd3 is the external power supply for pb14 to pb15 and pd8 to pd15 i/o pins (the i/o ground pin is internally connected to vss). for those pins all v dd supply references in this table are related to their given vddsdx power supply. symbol parameter conditions min max unit v ol (2) 2. the i io current sunk by the device must always resp ect the absolute maximum rating specified in table 20 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (3) i io = +8 ma 2.7 v < v dd < 3.6 v 3. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (4) 4. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 20 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ?0.4 - v ol (2) output low level voltage for an i/o pin ttl port (3) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v oh (4) output high level voltage for an i/o pin 2.4 - v ol (2)(5) 5. data based on design simulation. output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v oh (4)(5) output high level voltage for an i/o pin v dd ?1.3 - v ol (2)(5) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v -0.4 v oh (4)(5) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (2) output low level voltage for a ftf i/o pins in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v -0.4 electrical characteristics stm32f37x 86/128 doc id 022691 rev 3 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 21 and ta bl e 5 4 , respectively. unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . table 54. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2)(3) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) cl = 50 pf, v dd = 2 v to 3.6 v 2mhz t f(io)out output high to low level fall time 12 ns t r(io)out output low to high level rise time 34 t extipw pulse width of external signals detected by the exti controller 10 ns 1. the i/o speed is configured using the ospeedrx[1:0] bits . refer to the rm0313 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 21 . 3. guaranteed by design, not tested in production. 4. the i/o speed configuration is bypass ed in fm+ i/o mode. refer to the stm32f37xx and stm32f38xx reference manual rm0313 for a description of fm+ i/o mode configuration stm32f37x electrical characteristics doc id 022691 rev 3 87/128 figure 21. i/o ac characteristics definition 6.3.15 nrst characteristics nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 5 2 ). unless otherwise specified, the parameters given in ta bl e 5 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 2 2 . ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) ?? 2/3)t and if the duty cycle is (45-55%) ? 10 % 50% 90% when loaded by 50pf t t r(io)out table 55. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage 0.3v dd +0.07 (1) v v ih(nrst) (1) nrst input high level voltage 0.445 v dd + 0.398 (1) 1. data based on design simulati on only. not tested in production. v hys(nrst) (1) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimal (~10% order). v in ?? v ss 25 40 55 k ? v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 500 ns electrical characteristics stm32f37x 88/128 doc id 022691 rev 3 figure 22. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 55 . otherwise the reset will not be taken into account by the device. - 3 6 2 0 5 . 2 3 4 6 $ $ & i l t e r ) n t e r n a l 2 e s e t ? & % x t e r n a l r e s e t c i r c u i t stm32f37x electrical characteristics doc id 022691 rev 3 89/128 6.3.16 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 5 6 are derived from tests performed under ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta b l e 2 2 . the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 5 6 . refer also to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 56. i 2 c characteristics (1) symbol parameter standard mode fast mode fast mode plus unit min max min max min max t w(scll) scl clock low time 4.7 1.3 0.5 s t w(sclh) scl clock high time 4.0 0.6 0.26 t su(sda) sda setup time 250 100 50 ns t h(sda) sda data hold time 0 (2) 3450 (3) 0 (2) 900 (3) 0 (4) 450 (3) t r(sda) t r(scl) sda and scl rise time 1000 300 120 t f(sda) t f(scl) sda and scl fall time 300 300 120 t h(sta) start condition hold time 4.0 0.6 0.26 s t su(sta) repeated start condition setup time 4.7 0.6 0.26 t su(sto) stop condition setup time 4.0 0.6 0.26 ? s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 0.5 ? s c b capacitive load for each bus line 400 400 550 pf 1. the i 2 c characteristics are the requirements from i 2 c bus specification rev03. t hey are guaranteed by design when i2cx_timing register is correctly progr ammed (refer to reference manual). th ese characteristics are not tested in production. 2. the device must internally provide a hol d time of at least 300ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl. 3. the maximum data hold time has only to be met if the in terface does not stretch the low period of scl signal. 4. the device must internally provide a hol d time of at least 120ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl. electrical characteristics stm32f37x 90/128 doc id 022691 rev 3 figure 23. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 57. i 2 c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t sp pulse width of spikes that are suppressed by the analog filter 50 260 ns - 3 6 3 4 ! 2 4 3 $ ! ) # b u s 2 6 $ $ 6 $ $ - # 5 3 $ ! 3 # , t f 3 $ ! t r 3 $ ! 3 # , t h 3 4 ! t w 3 # , ( t w 3 # , , t s u 3 $ ! t r 3 # , t f 3 # , t h 3 $ ! 3 4 ! 2 4 2 % 0 % ! 4 % $ 3 4 ! 2 4 t s u 3 4 ! t s u 3 4 / 3 4 / 0 t w 3 4 / 3 4 ! 2 stm32f37x electrical characteristics doc id 022691 rev 3 91/128 spi/i 2 s characteristics unless otherwise specified, the parameters given in ta bl e 5 8 for spi or in ta bl e 5 9 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 2 2 . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 58. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) (1) spi clock frequency master mode 18 mhz slave mode 18 t r(sck) t f(sck) (1) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) (1) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. data based on characterization results, not tested in production. nss setup time slave mode 2tpclk ns t h(nss) (1) nss hold time slave mode 4tpclk t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 - 3 tpclk/2 + 3 t su(mi) (1) t su(si) (1) data input setup time master mode 5.5 slave mode 6.5 t h(mi) (1) data input hold time master mode 5 t h(si) (1) slave mode 5 t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 24 mhz 0 4tpclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. data output disable time slave mode 0 24 t v(so) (1) data output valid time slave mode (after enable edge) 39 t v(mo) (1) data output valid time master mode (after enable edge) 3 t h(so) (1) data output hold time slave mode (after enable edge) 15 t h(mo) (1) master mode (after enable edge) 4 electrical characteristics stm32f37x 92/128 doc id 022691 rev 3 figure 24. spi timing diagram - slave mode and cpha = 0 figure 25. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at 0.5v dd level and with external c l = 30 pf . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm32f37x electrical characteristics doc id 022691 rev 3 93/128 figure 26. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd level and with external c l = 30 pf . a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / electrical characteristics stm32f37x 94/128 doc id 022691 rev 3 table 59. i 2 s characteristics symbol parameter conditions min max unit ducy(sck) (1) i2s slave input clock duty cycle slave mode 30 70 % f ck (1) 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.528 1.539 mhz slave mode 0 12.288 t r(ck) (1) t f(ck) i 2 s clock rise and fall time capacitive load c l =30pf 8 ns t v(ws) (1) ws valid time master mode 4 t h(ws) (1) ws hold time master mode 4 t su(ws) (1) ws setup time slave mode 2 t h(ws) (1) ws hold time slave mode t w(ckh) (1) i2s clock high time master f pclk = 16 mhz, audio frequency = 48 khz 306 t w(ckl) (1) i2s clock low time 312 t su(sd_mr) (1) data input setup time master receiver 6 t su(sd_sr) (1) slave receiver 3 t h(sd_mr) (1) data input hold time master receiver 1.5 t h(sd_sr) (1) slave receiver 1.5 t v(sd_st) (1) data output valid time slave transmitter (after enable edge) 16 t h(sd_st) (1) data output hold time slave transmitter (after enable edge) 16 t v(sd_mt) (1) data output valid time master transmitter (after enable edge) 2 t h(sd_mt) (1) data output hold time master transmitter (after enable edge) 0 1. data based on design simulation, not tested in production. stm32f37x electrical characteristics doc id 022691 rev 3 95/128 figure 27. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd level and with external c l = 30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 28. i 2 s master timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd level and with external c l = 30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) electrical characteristics stm32f37x 96/128 doc id 022691 rev 3 6.3.17 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 6 0 are preliminary values derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 2 2 . note: it is recommended to perform a calibration after each power-up. table 60. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 (1) 220 (1) a f adc adc clock frequency 0.6 14 mhz f s (2) sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain conversion voltage range 0 (v ssa or v ref- tied to ground) v ref+ v r src (2) signal source impedance see equation 1 and ta bl e 6 1 for details 50 k ? r adc (2) sampling switch resistance 1 k ? c adc (2) internal sample and hold capacitor 8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 14 mhz 0.214 s 2 (3) 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (3) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 60 stm32f37x electrical characteristics doc id 022691 rev 3 97/128 equation 1: r src max formula the formula above ( equation 1 ) is used to determine the maximum external signal source impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 61. r src max for f adc = 14 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r src max (k ? ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 50 239.5 17.1 50 table 62. adc accuracy (1)(2) (3) 1. adc dc accuracy values are m easured after internal calibration. symbol parameter test conditions typ max (4) unit et total unadjusted error f adc = 14 mhz, r src < 10 k ? , v dda = 3 v to 3.6 v t a = 25 c 1.3 3 lsb eo offset error 1 2 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 et total unadjusted error f adc = 14 mhz, r src < 10 k ? , v dda = 2.7 v to 3.6 v t a = -40 to 105 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 et total unadjusted error f adc = 14 mhz, r src < 10 k ? , v dda = 2.4 v to 3.6 v t a = 25 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 r src t s f adc c adc 2 n2 + ?? ln ? ? ------------------------------------------------------------- - r adc ? ? electrical characteristics stm32f37x 98/128 doc id 022691 rev 3 figure 29. adc accuracy characteristics figure 30. typical connection diagram using the adc 1. refer to ta b l e 6 0 for the values of r src , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 9 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 2. adc accuracy vs. negative injection current: injecti ng a negative current on any analog input pins should be avoided as this significantly re duces the accuracy of the conver sion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current with in the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa - 3 6 1lsb ideal v dda - 3 6 v dd ainx i l 1 a 0.6 v v t 2 3 2 # c parasitic 3 2 # 0.6 v v t r adc (1) 12-bit converter c adc (1) sample and hold adc converter 7 stm32f37x electrical characteristics doc id 022691 rev 3 99/128 6.3.18 dac elect rical specifications table 63. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 2.4 - 3.6 v v ref+ reference supply voltage 2.4 - 3.6 v v ref+ must always be below v dda v ssa ground 0 - 0 v r load (1) resistive load with buffer on 5 - k ? r o (1) impedance output with buffer off -- 15 k ? when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m ? c load (1) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x155) and (0xeab) at v ref+ = 2.4 v dac_out max (1) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off -0.5 mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off -v ref+ ? 1lsb v i ddvref+ (3) dac dc current consumption in quiescent mode (standby mode) - 220 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (3) dac dc current consumption in quiescent mode (2) - 380 a with no load, middle code (0x800) on the inputs - 480 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (3) differential non linearity difference between two consecutive code-1lsb) - 0.5 lsb given for the dac in 10-bit configuration -2 lsb given for the dac in 12-bit configuration inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1lsb given for the dac in 10-bit configuration -- 4lsb given for the dac in 12-bit configuration electrical characteristics stm32f37x 100/128 doc id 022691 rev 3 figure 31. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10mv -- 3lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (3) gain error - - 0.5 % given for the dac in 12bit configuration t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb -3 4 sc load ? 50 pf, r load ? 5 k ? update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/sc load ? 50 pf, r load ? 5 k ? t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) - 6.5 10 s c load ? 50 pf, r load ? 5 k ? input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement --67 -40 dbno r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. quiescent mode refers to the state of the dac keeping a steady value on the output, so no dynamic consumption is involved. 3. guaranteed by characterizati on, not tested in production. table 63. dac characteristics (continued) symbol parameter min typ max unit comments r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157 stm32f37x electrical characteristics doc id 022691 rev 3 101/128 6.3.19 comparator characteristics table 64. comparator characteristics symbol parameter conditions min typ max (1) unit v dda analog supply voltage 2 3.6 v v in comparator input voltage range 0v dda v bg scaler input voltage 1.2 v sc scaler offset voltage 5 10 mv t s_sc scaler startup time from power down 0.1 ms t start comparator startup time startup time to reach propagation delay specification 60 s t d propagation delay for 200 mv step with 100 mv overdrive ultra-low power mode 2 4.5 s low power mode 0.7 1.5 medium power mode 0.3 0.6 high speed mode v dda ? 2.7 v 50 100 ns ? v dda ? 2.7 v 100 240 propagation delay for full range step with 100 mv overdrive ultra-low power mode 2 7 s low power mode 0.7 2.1 medium power mode 0.3 1.2 high speed mode v dda ? 2.7 v 90 180 ns ? v dda ? 2.7 v 110 300 v offset comparator offset error ? 4 ? 10 mv dv offset /dt offset error temperature coefficient 18 v/c i dd(comp) comp current consumption ultra-low power mode 1.2 1.5 a low power mode 3 5 medium power mode 10 15 high speed mode 75 100 electrical characteristics stm32f37x 102/128 doc id 022691 rev 3 v hys comparator hysteresis no hysteresis (compxhyst[1:0]=00) 0 mv low hysteresis (compxhyst[1:0]=01) high speed mode 3 8 13 all other power modes 510 medium hysteresis (compxhyst[1:0]=10) high speed mode 7 15 26 all other power modes 919 high hysteresis (compxhyst[1:0]=11) high speed mode 18 31 49 all other power modes 19 40 1. guaranteed by design, not tested in production. table 64. comparator characteristics (continued) symbol parameter conditions min typ max (1) unit stm32f37x electrical characteristics doc id 022691 rev 3 103/128 6.3.20 temperature sen sor characteristics 6.3.21 v bat monitoring characteristics 6.3.22 timer characteristics the parameters given in ta bl e 6 8 are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 65. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 66. ts characteristics symbol parameter min typ max unit t l v sense linearity with temperature ? 1 ? 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) 1. guaranteed by design, not tested in production. startup time 4 10 s t s_temp (2)(1) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s table 67. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k ? q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q -1 - +1 % t s_vbat (2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 5- -s electrical characteristics stm32f37x 104/128 doc id 022691 rev 3 table 68. timx (1) (2) characteristics 1. timx is used as a general term to refer to the tim2, tim3, tim4, tim5, tim6, tim7, tim12, tim13, tim14, tim15, tim16 , tim17, tim18 and tim19 timers. 2. data based on characterization results, not tested in production. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 72 mhz 13.9 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 0 24 mhz res tim timer resolution timx (except tim2) 16 bit tim2 32 t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s t max_count maximum possible count with 32-bit counter 65536 65536 t timxclk f timxclk = 72 mhz 59.65 s table 69. iwdg min/max timeout period at 40 khz (lsi) (1)(2) 1. these timings are given for a 40 khz clock but the mi crocontroller?s internal rc frequency can va ry from 30 to 60 khz. moreover, given an exac t rc oscillator frequency, the exac t timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. 2. data based on characterization results, not tested in production. prescaler divider pr[2:0] bits min timeout (ms) rl[11:0]= 0x000 max timeout (ms) rl[11:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 table 70. wwdg min-max timeout value @72 mhz (pclk) prescaler wdgtb min timeout value max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 stm32f37x electrical characteristics doc id 022691 rev 3 105/128 6.3.23 usb characteristics table 71. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s table 72. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 full-speed electrical specification, the usb_dp (d+) pin should be pulled up with a 1.5 k ? resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32f3xxx usb functionality is ensured down to 2.7 v but not the fu ll usb electrical characteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by design, not tested in production. differential input sensitivity (for usb compliance) i(usb_dp, usb_dm) 0.2 v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k ? to 3.6 v (5) 5. r l is the load connected on the usb drivers 0.3 v v oh static output level high r l of 15 k ? to v ss (5) 2.8 3.6 electrical characteristics stm32f37x 106/128 doc id 022691 rev 3 figure 32. usb timings: definition of data signal rise and fall time 6.3.24 can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). 6.3.25 sdadc characteristics ai14137 t f differen tial data l ines v ss v cr s t r crossover points table 73. usb: full-speed electrical characteristics (1) symbol parameter conditions min typ max unit driver characteristics t r rise time (2) c l = 50 pf 4 - 20 ns t f fall time (2) c l = 50 pf 4 - 20 ns t rfm rise/ fall time matching t r /t f 90 - 110 % v crs output signal crossover voltage 1.3 - 2.0 v output driver impedance (3) z drv driving high and low 28 40 44 ? 1. guaranteed by design, not tested in production. 2. measured from 10% to 90% of the data signal. for more detail ed informations, please refer to usb specification - chapter 7 (version 2.0). 3. no external termination series resi stors are required on usb_dp (d+) and us b_dm (d-), the matching impedance is already included in the embedded driver. table 74. sdadc characteristics (1) symbol parameter conditions min typ max unit note v ddsdx power supply slow mode (f adc = 1.5 mhz) 2.2 v dda v fast mode (f adc = 6 mhz) 2.4 v dda f adc sdadc clock frequency slow mode (f adc = 1.5 mhz) 0.5 1.5 1.65 mhz fast mode (f adc = 6 mhz) 0.5 6 6.3 v refsd+ positive ref. voltage 1.1 v ddsdx v v refsd- negative ref. voltage v ssa v stm32f37x electrical characteristics doc id 022691 rev 3 107/128 i ddsdx supply current (v ddsdx = 3.3 v) fast mode (f adc = 6 mhz) 800 1200 a slow mode (f adc = 1.5 mhz) 600 standby 200 power down 2.5 sd_adc off 1 v ain common input voltage range single ended mode (zero reference) v ssa v refsd+ /gain v voltage on ainp or ainn pin single ended offset mode v ssa v refsd+ /gain/2 differential mode v ssa v ddsdx v diff differential input voltage differential mode only -v ref sd+/ gain/2 v refsd+ / gain/2 differential voltage between ainp and ainn f s sampling rate slow mode (f adc = 1.5 mhz) 4.166 khz f adc /360 slow mode one channel only (f adc = 1.5 mhz) 12.5 f adc /120 fast mode multiplexed channel (f adc = 6 mhz) 16.66 f adc /360 fast mode one channel only (f adc = 6 mhz) 50 f adc /120 t conv conversion time 1/fs s rain analog input impedance one channel, gain = 0.5, f adc = 1.5 mhz 540 k ? see reference manual for detailed description one channel, gain = 0.5, f adc = 6 mhz 135 one channel, gain = 8, f adc = 6 mhz 47 t calib calibration time f adc = 6 mhz, one offset calibration 5120 s 30720/f adc t stab stabilization time from power down f adc = 6 mhz 100 s 600/f adc , 75/f adc if slowck =1 t standby wakeup from standby time f adc = 6 mhz 50 s 300/f adc f adc = 1.5 mhz 50 75/f adc if slowck =1 table 74. sdadc characteristics (continued) (1) symbol parameter conditions min typ max unit note electrical characteristics stm32f37x 108/128 doc id 022691 rev 3 eo offset error differential mode gain = 1 f adc = 1.5 mhz v ddsdx = 3.3 v refsd+ = 3.3 110 uv after offset calibration f adc = 6mhz v refsd+ = 1.2 110 v refsd+ = 3.3 100 gain = 8 f adc = 6mhz v refsd+ = 1.2 70 v refsd+ = 3.3 100 f adc = 1.5 mhz v refsd+ = 3.3 90 single ended mode gain = 1 v refsd+ = 1.2 2100 v refsd+ = 3.3 2000 gain = 8 v refsd+ = 1.2 1500 v refsd+ = 3.3 1800 dvoffsett emp offset drift with temperature differential or single ended mode, gain = 1, v ddsdx = 3.3 v 10 15 uv/k eg gain error all gains, differential mode, single ended mode -2.4 -2.7 -3.1 % egt gain drift with temperature gain = 1, differential mode, single ended mode 0 ppm/ k table 74. sdadc characteristics (continued) (1) symbol parameter conditions min typ max unit note stm32f37x electrical characteristics doc id 022691 rev 3 109/128 el integral linearity error differential mode gain = 1 v ddsdx = 3.3 v refsd+ = 1.2 16 lsb v refsd+ = 3.3 14 gain = 8 v refsd+ = 1.2 26 v refsd+ = 3.3 14 single ended mode gain = 1 v refsd+ = 1.2 31 v refsd+ = 3.3 23 gain = 8 v refsd+ = 1.2 80 v refsd+ = 3.3 35 ed differential linearity error differential mode gain = 1 v ddsdx = 3.3 v refsd+ = 1.2 2.4 lsb v refsd+ = 3.3 1.8 gain = 8 v refsd+ = 1.2 3.6 v refsd+ = 3.3 2.9 single ended mode gain = 1 v refsd+ = 1.2 3.2 v refsd+ = 3.3 2.8 gain = 8 v refsd+ = 1.2 4.1 v refsd+ = 3.3 3.3 table 74. sdadc characteristics (continued) (1) symbol parameter conditions min typ max unit note electrical characteristics stm32f37x 110/128 doc id 022691 rev 3 snr (4) signal to noise ratio differential mode gain = 1 f adc = 1.5 mhz v ddsdx = 3.3 v refsd+ = 3.3 (2) 84 85 db f adc = 6 mhz v refsd+ = 1.2 (3) 86 88 v refsd+ = 3.3 88 92 gain = 8 f adc = 6 mhz v refsd+ = 1.2 (3) 76 78 v refsd+ = 3.3 82 86 f adc = 1.5 mhz v refsd+ = 3.3 (2) 76 80 single ended mode gain = 1 f adc = 1.5mhz v refsd+ = 3.3 80 84 f adc = 6mhz v refsd+ = 1.2 (3) 77 81 v refsd+ = 3.3 85 90 gain = 8 f adc = 6mhz v refsd+ = 1.2 (3) 66 71 v refsd+ = 3.3 74 78 table 74. sdadc characteristics (continued) (1) symbol parameter conditions min typ max unit note stm32f37x electrical characteristics doc id 022691 rev 3 111/128 sinad (4) signal to noise and distortion ratio differential mode gain =1 f adc = 1.5 mhz v ddsdx = 3.3 v refsd+ = 3.3 (2) 76 77 db enob = sinad/6.0 2 -0.292 f adc = 6 mhz v refsd+ = 1.2 (3) 75 76 v refsd+ = 3.3 76 77 gain =8 f adc = 6 mhz v refsd+ = 1.2 (3) 70 74 v refsd+ = 3.3 79 85 f adc = 1.5 mhz v refsd+ = 3.3 (2) 75 81 single ended mode gain =1 f adc = 1.5mhz v refsd+ = 3.3 72 73 f adc = 6mhz v refsd+ = 1.2 (3) 68 71 v refsd+ = 3.3 72 73 gain =8 f adc = 6mhz v refsd+ = 1.2 (3) 60 64 v ref = 3.3 67 72 thd (4) to t a l harmonic distortion differential mode gain =1 f adc = 1.5 mhz v ddsdx = 3.3 v refsd+ = 3.3 (2) -77 -76 db f adc = 6mhz v refsd+ = 1.2 (3) -77 -76 v refsd+ = 3.3 -77 -76 gain =8 f adc = 6mhz v refsd+ = 1.2 (3) -85 -70 v refsd+ = 3.3 -93 -80 f adc = 1.5 mhz v refsd+ = 3.3 (2) -93 -83 single ended mode gain =1 f adc = 6mhz v refsd+ = 1.2 (3) -72 -68 v refsd+ = 3.3 -74 -72 gain =8 f adc = 6mhz v refsd+ = 1.2 (3) -66 -61 v refsd+ = 3.3 -75 -70 1. data based on characterization results, not tested in production. table 74. sdadc characteristics (continued) (1) symbol parameter conditions min typ max unit note electrical characteristics stm32f37x 112/128 doc id 022691 rev 3 2. for f adc lower than 5 mhz, there will be a performance degradation of around 2 db due to flicker noise increase. 3. if the reference value is lower than 2.4 v, there will be a performance degradation proporti onal to the reference supply drop, according to this formula: 20*log10(v ref /2.4) db 4. snr, thd, sinad parameters are valid for frequency band width 20hz - 1khz. input signal frequency is 300hz (for f adc =6mhz) and 100hz (for f adc =1.5mhz). table 75. vrefsd+ pin characteristics (1) symbol parameter conditions min typ max unit note v refint internal reference voltage buffered embedded reference voltage (1.2 v) 1.2 v see section 6.3.4: embedded reference voltage on page 58 embedded reference voltage amplified by factor 1.5 1.8 c vrefsd+ (2) reference voltage filtering capacitor v refsd+ = v refint 1000 10000 nf r vrefsd+ reference voltage input impedance fast mode (f adc = 6 mhz) 238 k ? see rm0313 reference manual for detailed description slow mode (f adc = 1.5 mhz) 952 1. data based on characterization results, not tested in production. 2. if internal reference volt age is selected then this capacitor is charged th rough internal resistance - typ. 300 ohm. if inte rnal reference source is selected through the reference voltage selection bits (refv<>?00? in sdadc_cr1 register), the application must first configure refv bits and then wait for capacitor charging. re commended waiting time is 3 ms if 1 f capacitor is used. stm32f37x package characteristics doc id 022691 rev 3 113/128 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. package characteristics stm32f37x 114/128 doc id 022691 rev 3 figure 33. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline 1. drawing is not to scale. a1 ba ll p a d corner top view s ide view bottom view a1 ba ll p a d corner e d e1 e fe d1 fd 0.50 0.10 a1 a a2 1.75 1.75 0.10 z x y a0c2_me b table 76. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.46 0.53 0.6 0.0181 0.0209 0.0236 a1 0.06 0.08 0.1 0.0024 0.0031 0.0039 a2 0.4 0.45 0.5 0.0157 0.0177 0.0197 b 0.2 0.25 0.3 0.0079 0.0098 0.0118 d 7 0.2756 d1 5.5 0.2165 e 7 0.2756 e1 5.5 0.2165 e 0.5 0.0197 fd 0.75 0.0295 fe 0.75 0.0295 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32f37x package characteristics doc id 022691 rev 3 115/128 figure 34. lqfp100 ?14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! table 77. lqpf100 ? 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 15.80 16.00 16.20 0.622 0.6299 0.6378 d1 13.80 14.00 14.20 0.5433 0.5512 0.5591 d3 12.00 0.4724 e 15.80 16.00 16.20 0.622 0.6299 0.6378 package characteristics stm32f37x 116/128 doc id 022691 rev 3 figure 35. recommended footprint 1. dimensions are in millimeters. e1 13.80 14.00 14.20 0.5433 0.5512 0.5591 e3 12.00 0.4724 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 77. lqpf100 ? 14 x 14 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 75 51 50 76 0.5 0. 3 16.7 14. 3 100 26 12. 3 25 1.2 16.7 1 a i14906 b stm32f37x package characteristics doc id 022691 rev 3 117/128 figure 36. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. ! ! ! 3 % ! 4 ) . ' 0 , ! . % c c c # b # c ! , , + ' ! 5 ' % 0 , ! . % m m ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . $ $ $ e % % % 7 ? - % ? 6 table 78. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 11.80 12.00 12.20 0.4646 0.4724 0.4803 d1 9.80 10.00 10.20 0.3858 0.3937 0.4016 d3 7.50 0.2953 package characteristics stm32f37x 118/128 doc id 022691 rev 3 figure 37. recommended footprint 1. dimensions are in millimeters. e 11.80 12.00 12.20 0.4646 0.4724 0.4803 e1 9.80 10.00 10.20 0.3858 0.3937 0.4016 e3 7.50 0.2953 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 78. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i b stm32f37x package characteristics doc id 022691 rev 3 119/128 figure 38. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + table 79. lqfp48 ? 7 x 7 mm, low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 8.80 9.00 9.20 0.3465 0.3543 0.3622 d1 6.80 7.00 7.20 0.2677 0.2756 0.2835 d3 5.50 0.2165 e 8.80 9.00 9.20 0.3465 0.3543 0.3622 e1 6.80 7.00 7.20 0.2677 0.2756 0.2835 e3 5.50 0.2165 package characteristics stm32f37x 120/128 doc id 022691 rev 3 figure 39. recommended footprint 1. dimensions are in millimeters. e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 79. lqfp48 ? 7 x 7 mm, low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i d stm32f37x package characteristics doc id 022691 rev 3 121/128 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 22: general operating conditions on page 55 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in ? c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org table 80. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp48 - 7 7 mm 55 thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient bga100 - 7 x 7 mm 59 package characteristics stm32f37x 122/128 doc id 022691 rev 3 7.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f 37x at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 3 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 2 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 3 8 ma 0.4 v + 2 20 ma 1.3 v = 61.6 mw this gives: p intmax = 175 mw and p iomax = 61.6 mw: p dmax = 175+ 61.6 = 236.6 mw thus: p dmax = 236.6 mw using the values obtained in ta b l e 8 0 t jmax is calculated as follows: ? for lqfp64, 45c/w t jmax = 82 c + (45c/w 236.6 mw) = 82 c + 10.65 c = 92.65 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see section 8: part numbering ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 9 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 9 8 ma 0.4 v = 28.8 mw this gives: p intmax = 70 mw and p iomax = 28.8 mw: p dmax = 70 + 28.8 = 98.8 mw thus: p dmax = 98.8 mw stm32f37x package characteristics doc id 022691 rev 3 123/128 using the values obtained in ta b l e 8 0 t jmax is calculated as follows: ? for lqfp100, 46c/w t jmax = 115 c + (46c/w 98.8 mw) = 115 c + 4.54 c = 119.5 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see section 8: part numbering ). figure 40. lqfp64 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7 part numbering stm32f37x 124/128 doc id 022691 rev 3 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. table 81. ordering information scheme example :stm32f372r8t6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 372 = STM32F372XX 373 = stm32f373xx pin count c = 48 pins r = 64 pins v = 100 pins code size 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory c = 256 kbytes of flash memory package t = lqfp h = bga temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c options xxx = programmed parts tr = tape and real stm32f37x revision history doc id 022691 rev 3 125/128 9 revision history table 82. document revision history date revision changes 18-jun-2012 1 initial release. 07-sep-2012 2 added ?f? to all ?cortex-m4? occurences modified the shapes of figure 2: stm32f37x lqfp48 pinout to figure 4: stm32f37x lqfp100 pinout added two rows ?vrefsd+ - vddsd3? and ?vref+ - vdda? in table 19: voltage characteristics removed pb0 in footnote of table 19: voltage characteristics and in section 6.3.14: i/o port characteristics added a paragraph after ?...power up sequence? in table 6.2: absolute maximum ratings and after ?...in output mode? in i/o system current consumption corrected sdac_vref+ in figure 9: power supply scheme modified table 20: current characteristics added bga100 in table 22: general operating conditions added values in table 27: embedded internal reference voltage filled values in table 28: typical and maximum current consumption from vdd supply at vdd = 3.6 v filled values in table 29: typical and maximum current consumption from vdda supply filled values in table 30: typical and maximum vdd consumption in stop and standby modes removed table: ?typical and maximum vdda consumption in stop modes? filled values in table 31: typical and maximum vdda consumption in stop and standby modes added vbat values in table 32: typical and maximum current consumption from vbat supply added typ values in table 33: typical current consumption in run mode, code with data processing running from flash and table 34: typical current consumption in sleep mode, code running from flash or ram added max value in table 41: lse oscillator characteristics (flse = 32.768 khz) modified min and max values in table 42: hsi oscillator characteristics added values in table 37: low-power mode wakeup timings added class values in table 47: ems characteristics modified values in table 48: emi characteristics added values in table 49: esd absolute maximum ratings added class value in table 50: electrical sensitivities modified values and descriptions in table 51: i/o current injection susceptibility revision history stm32f37x 126/128 doc id 022691 rev 3 07-sep-2012 2 (cont?d) filled values in table 70: wwdg min-max timeout value @72 mhz (pclk) filled values in table 58: spi characteristics filled values in table 59: i2s characteristics replaced table 60: adc characteristics added values in table 74: sdadc characteristics modified footnote in table 75: vrefsd+ pin characteristics replaced ?ain? with ?src? in table 61: rsrc max for fadc = 14 mhz and figure 30: typical connection diagram using the adc reordered chapters and cover page features. added subsection to gpios in table 2: device overview aligned sram with usb in figure 1: block diagram added ?do not reconfigure...? sentence in section 3.9: general-purpose input/outputs (gpios) added table 7: stm32f37x i2c implementation added table 8: stm32f37x usart implementation merged spi and i2s into one section reshaped figure 5: stm32f37x bga100 pinout and removed adc10 added notes column, modified i/o structure values and pin, function names, removed tim1_tx & tim1_rx in table 11: stm32f37x pin definitions added the note ?do not reconfigure...? after table 11: stm32f37x pin definitions modified ?x_ck? occurences to ?i2sx_ck? in ta bl e 1 2 : alternate functions for port pa to table 17: alternate functions for port pf added two gp i/os in table 9: power supply scheme added caution after table 9: power supply scheme added max values in table 23: operating conditions at power- up / power-down modified (1) footnote in table 24: embedded reset and power control block characteristics added row to table 27: embedded internal reference voltage added the note ? it is recommended...? under table 51: i/o current injection susceptibility modified table 51: i/o current injection susceptibility modified temperature and current values in section 7.2.2: selecting the product temperature range added crystal epson-toyocom bullet under typical current consumption modified figure 9: power supply scheme removed boot 0 section modified table 73: usb: full-speed electrical characteristics table 82. document revision history date revision changes stm32f37x revision history doc id 022691 rev 3 127/128 21-dec-2012 3 updated table 2: device overview , capacitive sensing channels peripheral added. updated table 3: capacitive sensing gpios available on stm32f37x devices updated section 3.19: inter-integrated circuit interface (i2c) updated the function names in table 11: stm32f37x pin definitions updated table 20: current characteristics updated table 22: general operating conditions updated table 30: typical and maximum vdd consumption in stop and standby modes updated table 32: typical and maxi mum current consumption from vbat supply added figure 11: typical vbat current consumption (lse and rtc on/lsedrv[1:0]='00') updated table 33: typical current consumption in run mode, code with data processing running from flash table 34: typical current consumption in sleep mode, code running from flash or ram added table 35: switching output i/o current consumption added table 36: peripheral current consumption figure 16: hsi oscillator accu racy characterization results updated section 6.3.6: wakeup time from low-power mode updated table 37: low-power mode wakeup timings updated table 47: ems characteristics updated table 51: i/o current injection susceptibility updated table 52: i/o static characteristics updated figure 17: tc and tta i/o input characteristics - cmos port , figure 18: tc and tta i/o input characteristics - ttl port , figure 19: five volt tolerant (ft and ftf) i/o input characteristics - cmos port and figure 20: five volt tolerant (ft and ftf) i/o input characteristics - ttl port updated table 53: output voltage characteristics updated table 55: nrst pin characteristics updated table 54: i/o ac characteristics updated table 63: dac characteristics updated table 74: sdadc characteristics updated figure 7: lqfp100 ? 14 x 14 mm 100 pin low-profile quad flat package outline , figure 9: lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline and figure 11: lqfp48 ? 7 x 7 mm, 48 pin low-profile quad flat package outline updated table 21: lqfp100 ? 14 x 14 mm low-profile quad flat package mechanical data , table 22: lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data and table 23: lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data added figure 16: hsi oscillator accuracy characterization results table 82. document revision history date revision changes stm32f37x 128/128 doc id 022691 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 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